From 5fd50b6b198d7e086945ca0255ccc0757b31f748 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 22 Mar 2020 13:00:44 +0100 Subject: nb/intel/sandybridge: Add and use TC_DTP definition This register is specific to Ivy Bridge. This changes the binary because the operations get reordered, but it is equivalent. Change-Id: Ibc9127e0fc268466c13f7c5ac8d942543713ca32 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39759 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/northbridge/intel/sandybridge/mchbar_regs.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'src/northbridge/intel/sandybridge/mchbar_regs.h') diff --git a/src/northbridge/intel/sandybridge/mchbar_regs.h b/src/northbridge/intel/sandybridge/mchbar_regs.h index a8ae9c53a9..cf29155f35 100644 --- a/src/northbridge/intel/sandybridge/mchbar_regs.h +++ b/src/northbridge/intel/sandybridge/mchbar_regs.h @@ -215,6 +215,10 @@ #define TC_RAP_ch(ch) Cx(0x4004, ch) /* Timings: Regular access */ #define TC_RWP_ch(ch) Cx(0x4008, ch) /* Timings: Read / Write */ #define TC_OTHP_ch(ch) Cx(0x400c, ch) /* Timings: Other parameters */ + +/** WARNING: Only applies to Ivy Bridge! */ +#define TC_DTP_ch(ch) Cx(0x4014, ch) /** Timings: Debug parameters */ + #define SCHED_SECOND_CBIT_ch(ch) Cx(0x401c, ch) /* More chicken bits */ #define SCHED_CBIT_ch(ch) Cx(0x4020, ch) /* Chicken bits in scheduler */ #define SC_ROUNDT_LAT_ch(ch) Cx(0x4024, ch) /* Round-trip latency per rank */ @@ -280,6 +284,10 @@ #define TC_RAP 0x4c04 /* Timings: Regular access */ #define TC_RWP 0x4c08 /* Timings: Read / Write */ #define TC_OTHP 0x4c0c /* Timings: Other parameters */ + +/** WARNING: Only applies to Ivy Bridge! */ +#define TC_DTP 0x4c14 /** Timings: Debug parameters */ + #define SCHED_SECOND_CBIT 0x4c1c /* More chicken bits */ #define SCHED_CBIT 0x4c20 /* Chicken bits in scheduler */ #define SC_ROUNDT_LAT 0x4c24 /* Round-trip latency per rank */ -- cgit v1.2.3