From a71bdc318195b864c427cddc60e69a6145a8ab28 Mon Sep 17 00:00:00 2001 From: Vladimir Serbinenko Date: Sat, 30 Aug 2014 00:35:39 +0200 Subject: intel/gma: consolidate vbt code Change-Id: I80b7facfb9cc9f642dd1c766884dc23da1aab2c8 Signed-off-by: Vladimir Serbinenko Reviewed-on: http://review.coreboot.org/6800 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan --- .../intel/sandybridge/gma_sandybridge_lvds.c | 108 +++------------------ 1 file changed, 16 insertions(+), 92 deletions(-) (limited to 'src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c') diff --git a/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c index 77c5b6f5fc..08cceea383 100644 --- a/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c +++ b/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c @@ -26,7 +26,6 @@ #include #include -#include #include "gma.h" #include "chip.h" #include @@ -36,54 +35,6 @@ #if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) -static size_t generate_vbt(const struct northbridge_intel_sandybridge_config *conf, - void *vbt) -{ - struct vbt_header *head = vbt; - struct bdb_header *bdb_head; - struct bdb_general_features *genfeat; - u8 *ptr; - - memset(head, 0, sizeof (*head)); - - memcpy(head->signature, "$VBT SNB/IVB-MOBILE ", 20); - head->version = 100; - head->header_size = sizeof (*head); - head->bdb_offset = sizeof (*head); - - bdb_head = (struct bdb_header *) (head + 1); - memset(bdb_head, 0, sizeof (*bdb_head)); - memcpy(bdb_head->signature, "BIOS_DATA_BLOCK ", 16); - bdb_head->version = 0xa8; - bdb_head->header_size = sizeof (*bdb_head); - - ptr = (u8 *) (bdb_head + 1); - - ptr[0] = BDB_GENERAL_FEATURES; - ptr[1] = sizeof (*genfeat); - ptr[2] = sizeof (*genfeat) >> 8; - ptr += 3; - - genfeat = (struct bdb_general_features *) ptr; - memset(genfeat, 0, sizeof (*genfeat)); - genfeat->panel_fitting = 3; - genfeat->flexaim = 1; - genfeat->download_ext_vbt = 1; - genfeat->enable_ssc = conf->gpu_use_spread_spectrum_clock; - genfeat->ssc_freq = !conf->gpu_link_frequency_270_mhz; - genfeat->rsvd10 = 0x4; - genfeat->legacy_monitor_detect = 1; - genfeat->int_crt_support = 1; - genfeat->dp_ssc_enb = 1; - - ptr += sizeof (*genfeat); - - bdb_head->bdb_size = ptr - (u8 *)bdb_head; - head->vbt_size = ptr - (u8 *)head; - head->vbt_checksum = 0; - return ptr - (u8 *)head; -} - static void train_link(u32 mmio) { /* Clear interrupts. */ @@ -171,7 +122,7 @@ static void power_port(u32 mmio) read32(mmio + 0x000e1180); // = 0x40000002 } -int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, +int i915lightup_sandy(const struct i915_gpu_controller_info *info, u32 physbase, u16 piobase, u32 mmio, u32 lfb) { int i; @@ -187,7 +138,7 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, u32 pixel_n = 1; u32 pixel_m1 = 1; u32 pixel_m2 = 1; - u32 link_frequency = info->gpu_link_frequency_270_mhz ? 270000 : 162000; + u32 link_frequency = info->link_frequency_270_mhz ? 270000 : 162000; u32 data_m1; u32 data_n1 = 0x00800000; u32 link_m1; @@ -252,7 +203,7 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, hfront_porch = edid.hso; vfront_porch = edid.vso; - target_frequency = info->gpu_lvds_dual_channel ? edid.pixel_clock + target_frequency = info->lvds_dual_channel ? edid.pixel_clock : (2 * edid.pixel_clock); #if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) vga_textmode_init(); @@ -323,7 +274,7 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, link_m1 = ((uint64_t)link_n1 * edid.pixel_clock) / link_frequency; data_m1 = ((uint64_t)data_n1 * 18 * edid.pixel_clock) - / (link_frequency * 8 * (info->gpu_lvds_num_lanes ? : 4)); + / (link_frequency * 8 * (info->lvds_num_lanes ? : 4)); printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", hactive, vactive); @@ -335,10 +286,10 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, hsync, vsync); printk(BIOS_DEBUG, "Front porch %d x %d\n", hfront_porch, vfront_porch); - printk(BIOS_DEBUG, (info->gpu_use_spread_spectrum_clock + printk(BIOS_DEBUG, (info->use_spread_spectrum_clock ? "Spread spectrum clock\n" : "DREF clock\n")); printk(BIOS_DEBUG, - info->gpu_lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); + info->lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); printk(BIOS_DEBUG, "Polarities %d, %d\n", hpolarity, vpolarity); printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", @@ -355,12 +306,12 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, write32(mmio + PCH_LVDS, (hpolarity << 20) | (vpolarity << 21) - | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_DETECTED); write32(mmio + BLC_PWM_CPU_CTL2, (1 << 31)); - write32(mmio + PCH_DREF_CONTROL, (info->gpu_use_spread_spectrum_clock + write32(mmio + PCH_DREF_CONTROL, (info->use_spread_spectrum_clock ? 0x1002 : 0x400)); mdelay(1); write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS @@ -371,18 +322,18 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, write32(mmio + PCH_DPLL_SEL, 8); write32(mmio + _PCH_DPLL(0), DPLL_VCO_ENABLE | DPLLB_MODE_LVDS - | (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + | (info->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | (0x10000 << (pixel_p1 - 1)) - | ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13) + | ((info->use_spread_spectrum_clock ? 3 : 0) << 13) | (0x1 << (pixel_p1 - 1))); mdelay(1); write32(mmio + _PCH_DPLL(0), DPLL_VCO_ENABLE | DPLLB_MODE_LVDS - | (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + | (info->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | (0x10000 << (pixel_p1 - 1)) - | ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13) + | ((info->use_spread_spectrum_clock ? 3 : 0) << 13) | (0x1 << (pixel_p1 - 1))); /* Re-lock the registers. */ write32(mmio + PCH_PP_CONTROL, @@ -390,7 +341,7 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, write32(mmio + PCH_LVDS, (hpolarity << 20) | (vpolarity << 21) - | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_DETECTED); @@ -487,7 +438,7 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, write32(mmio + PCH_LVDS, LVDS_PORT_ENABLE | (hpolarity << 20) | (vpolarity << 21) - | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_DETECTED); @@ -522,35 +473,8 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, #endif /* Linux relies on VBT for panel info. */ - optionrom_header_t *oh = (void *)PCI_VGA_RAM_IMAGE_START; - optionrom_pcir_t *pcir; - size_t vbt_size; - size_t fake_oprom_size; - struct device *dev; - - dev = dev_find_slot(0, PCI_DEVFN(2, 0)); - - memset(oh, 0, 8192); - - oh->signature = OPROM_SIGNATURE; - oh->pcir_offset = 0x40; - oh->vbt_offset = 0x80; - - pcir = (void *)(PCI_VGA_RAM_IMAGE_START + 0x40); - pcir->signature = 0x52494350; // PCIR - pcir->vendor = dev->vendor; - pcir->device = dev->device; - pcir->length = sizeof(*pcir); - pcir->revision = dev->class; - pcir->classcode[0] = dev->class >> 8; - pcir->classcode[1] = dev->class >> 16; - pcir->classcode[2] = dev->class >> 24; - pcir->indicator = 0x80; - - vbt_size = generate_vbt (info, (void *)(PCI_VGA_RAM_IMAGE_START + 0x80)); - fake_oprom_size = (0x80 + vbt_size + 511) / 512; - oh->size = fake_oprom_size; - pcir->imagelength = fake_oprom_size; + generate_fake_intel_oprom(info, dev_find_slot(0, PCI_DEVFN(2, 0)), + "$VBT SNB/IVB-MOBILE "); return 1; } -- cgit v1.2.3