From 1dd448c0cfe00208e068cdab6fc20f983c9df0c4 Mon Sep 17 00:00:00 2001 From: Vagiz Trakhanov Date: Thu, 28 Sep 2017 14:42:11 +0000 Subject: nb/intel: Add Ivy Bridge Server (Xeon-E3v2) PCI IDs Change-Id: I1899dbe9498a0cc83b65b4bc1c6c0a555637fd05 Signed-off-by: Vagiz Tarkhanov Reviewed-on: https://review.coreboot.org/21753 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/northbridge/intel/sandybridge/early_init.c | 1 + 1 file changed, 1 insertion(+) (limited to 'src/northbridge/intel/sandybridge/early_init.c') diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index 3580f3509d..2f1b790bcb 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -98,6 +98,7 @@ static void sandybridge_setup_graphics(void) case 0x0156: /* IvyBridge */ case 0x0162: /* IvyBridge */ case 0x0166: /* IvyBridge */ + case 0x016a: /* IvyBridge */ break; default: printk(BIOS_DEBUG, "Graphics not supported by this CPU/chipset.\n"); -- cgit v1.2.3