From 7c49cb8f9ca86e791c392da40e7f0d3cb7ed47f3 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 16 Mar 2020 23:17:32 +0100 Subject: nb/intel/sandybridge: Tidy up code and comments - Reformat some lines of code - Move MCHBAR registers and documentation into a separate file - Add a few missing macros - Rename some registers - Rewrite several comments - Use C-style comments for consistency - Rewrite some hex constants - Use HOST_BRIDGE instead of PCI_DEV(0, 0, 0) With BUILD_TIMELESS=1, this commit does not change the result of: - Asus P8Z77-V LX2 with native raminit. - Asus P8Z77-M PRO with MRC raminit. Change-Id: I6e113e48afd685ca63cfcb11ff9fcf9df6e41e46 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39599 Reviewed-by: Felix Held Reviewed-by: Patrick Rudolph Tested-by: build bot (Jenkins) --- src/northbridge/intel/sandybridge/acpi.c | 50 +++++++++++++++++--------------- 1 file changed, 27 insertions(+), 23 deletions(-) (limited to 'src/northbridge/intel/sandybridge/acpi.c') diff --git a/src/northbridge/intel/sandybridge/acpi.c b/src/northbridge/intel/sandybridge/acpi.c index 074e9413fa..d0434259d4 100644 --- a/src/northbridge/intel/sandybridge/acpi.c +++ b/src/northbridge/intel/sandybridge/acpi.c @@ -33,38 +33,39 @@ unsigned long acpi_fill_mcfg(unsigned long current) if (!dev) return current; - pciexbar_reg=pci_read_config32(dev, PCIEXBAR); + pciexbar_reg = pci_read_config32(dev, PCIEXBAR); - // MMCFG not supported or not enabled. + /* MMCFG not supported or not enabled */ if (!(pciexbar_reg & (1 << 0))) return current; switch ((pciexbar_reg >> 1) & 3) { - case 0: // 256MB - pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)); + case 0: /* 256MB */ + pciexbar = pciexbar_reg & (0xffffffffULL << 28); max_buses = 256; break; - case 1: // 128M - pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); + case 1: /* 128M */ + pciexbar = pciexbar_reg & (0xffffffffULL << 27); max_buses = 128; break; - case 2: // 64M - pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)); + case 2: /* 64M */ + pciexbar = pciexbar_reg & (0xffffffffULL << 26); max_buses = 64; break; - default: // RSVD + default: /* RSVD */ return current; } if (!pciexbar) return current; - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, - pciexbar, 0x0, 0x0, max_buses - 1); + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, pciexbar, 0, 0, + max_buses - 1); return current; } + static unsigned long acpi_create_igfx_rmrr(const unsigned long current) { const u32 base_mask = ~(u32)(MiB - 1); @@ -73,7 +74,7 @@ static unsigned long acpi_create_igfx_rmrr(const unsigned long current) if (!host) return 0; - const u32 bgsm = pci_read_config32(host, BGSM) & base_mask; + const u32 bgsm = pci_read_config32(host, BGSM) & base_mask; const u32 tolud = pci_read_config32(host, TOLUD) & base_mask; if (!bgsm || !tolud) return 0; @@ -89,7 +90,7 @@ static unsigned long acpi_fill_dmar(unsigned long current) unsigned long tmp; tmp = current; - current += acpi_create_dmar_drhd(current, 0, 0, IOMMU_BASE1); + current += acpi_create_dmar_drhd(current, 0, 0, GFXVT_BASE); current += acpi_create_dmar_ds_pci(current, 0, 2, 0); current += acpi_create_dmar_ds_pci(current, 0, 2, 1); acpi_dmar_drhd_fixup(tmp, current); @@ -104,34 +105,37 @@ static unsigned long acpi_fill_dmar(unsigned long current) } const unsigned long tmp = current; - current += acpi_create_dmar_drhd(current, - DRHD_INCLUDE_PCI_ALL, 0, IOMMU_BASE2); - current += acpi_create_dmar_ds_ioapic(current, - 2, PCH_IOAPIC_PCI_BUS, PCH_IOAPIC_PCI_SLOT, 0); + current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, VTVC0_BASE); + + current += acpi_create_dmar_ds_ioapic(current, 2, PCH_IOAPIC_PCI_BUS, + PCH_IOAPIC_PCI_SLOT, 0); + size_t i; for (i = 0; i < 8; ++i) - current += acpi_create_dmar_ds_msi_hpet(current, - 0, PCH_HPET_PCI_BUS, PCH_HPET_PCI_SLOT, i); + current += acpi_create_dmar_ds_msi_hpet(current, 0, PCH_HPET_PCI_BUS, + PCH_HPET_PCI_SLOT, i); + acpi_dmar_drhd_fixup(tmp, current); return current; } -unsigned long northbridge_write_acpi_tables(struct device *const dev, - unsigned long current, +unsigned long northbridge_write_acpi_tables(struct device *const dev, unsigned long current, struct acpi_rsdp *const rsdp) { - const u32 capid0_a = pci_read_config32(dev, 0xe4); + const u32 capid0_a = pci_read_config32(dev, CAPID0_A); if (capid0_a & (1 << 23)) return current; printk(BIOS_DEBUG, "ACPI: * DMAR\n"); + acpi_dmar_t *const dmar = (acpi_dmar_t *)current; + acpi_create_dmar(dmar, DMAR_INTR_REMAP, acpi_fill_dmar); current += dmar->header.length; current = acpi_align_current(current); - acpi_add_table(rsdp, dmar); + acpi_add_table(rsdp, dmar); current = acpi_align_current(current); printk(BIOS_DEBUG, "current = %lx\n", current); -- cgit v1.2.3