From 6fcd7b8eb1ee650daa939593e8cbb3939f7c1188 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sun, 3 Jun 2018 12:16:24 +0200 Subject: cpu/intel/model_206ax: Switch to POSTCAR_STAGE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Tested on Lenovo Thinkpad X220 with both native raminit and mrc.bin. Change-Id: I5e1a1175d79af4dc079a5a08a464eef08de0bcbf Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/26791 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/northbridge/intel/sandybridge/Makefile.inc | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/northbridge/intel/sandybridge/Makefile.inc') diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index d08b141b3d..3d8da0c4bc 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -46,4 +46,6 @@ romstage-y += ../../../arch/x86/walkcbfs.S smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c +postcar-y += ram_calc.c + endif -- cgit v1.2.3