From bfca67078cfddc18994fa6bbe9094a2ecca275a3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 22 Jul 2016 22:48:35 +0300 Subject: intel/sandybridge post-car: Redo MTRR settings and stack selection MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Adapt implementation from haswell to prepare for removal of HIGH_MEMORY_SAVE and moving on to RELOCATABLE_RAMSTAGE. With the change, CBMEM and SMM regions are set to WRBACK with MTRRs and romstage ram stack is moved to CBMEM. Also fixes regression of slower S3 resume path after commit 9b99152 intel/sandybridge: Use common ACPI S3 recovery Skipping low memory backup and using stage cache for ramstage decreases time spent on S3 resume path by 50 ms on samsung/lumpy. Change-Id: I2afee3662e73e8e629188258b2f4119e02d60305 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/15790 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/northbridge/intel/sandybridge/Kconfig | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/northbridge/intel/sandybridge/Kconfig') diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 2fb455159e..d7af9f2329 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -22,6 +22,7 @@ config NORTHBRIDGE_INTEL_SANDYBRIDGE select CPU_INTEL_MODEL_206AX select HAVE_DEBUG_RAM_SETUP select INTEL_GMA_ACPI + select RELOCATABLE_RAMSTAGE config NORTHBRIDGE_INTEL_IVYBRIDGE bool @@ -31,6 +32,7 @@ config NORTHBRIDGE_INTEL_IVYBRIDGE select CPU_INTEL_MODEL_306AX select HAVE_DEBUG_RAM_SETUP select INTEL_GMA_ACPI + select RELOCATABLE_RAMSTAGE if NORTHBRIDGE_INTEL_IVYBRIDGE || NORTHBRIDGE_INTEL_SANDYBRIDGE -- cgit v1.2.3