From 92fc072c2faf3d1be82f50ee3feda42461e9ac16 Mon Sep 17 00:00:00 2001 From: Alexander Couzens Date: Wed, 9 Mar 2016 14:36:46 +0100 Subject: northbridge/intel: move mrccache.c of sandybridge + haswell to common The sourcecode is 99% the same. Only two lines differ, but not in functionality. Also rename mrccache.c -> mrc_cache.c Tested-on: boot + suspend/resume on x220 Change-Id: I36f79d066336f223b608c70c847ea6ea6e4ad287 Signed-off-by: Alexander Couzens Reviewed-on: https://review.coreboot.org/14007 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/northbridge/intel/sandybridge/Kconfig | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/northbridge/intel/sandybridge/Kconfig') diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 9b90f36178..64f4a14c3f 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -18,6 +18,7 @@ config NORTHBRIDGE_INTEL_SANDYBRIDGE bool select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT + select NORTHBRIDGE_INTEL_COMMON_MRC_CACHE select CPU_INTEL_MODEL_206AX select HAVE_DEBUG_RAM_SETUP select INTEL_GMA_ACPI @@ -26,6 +27,7 @@ config NORTHBRIDGE_INTEL_IVYBRIDGE bool select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT + select NORTHBRIDGE_INTEL_COMMON_MRC_CACHE select CPU_INTEL_MODEL_306AX select HAVE_DEBUG_RAM_SETUP select INTEL_GMA_ACPI -- cgit v1.2.3