From cd7a70f4879ff6e0f3e334ddf1031ccf0c0d31cf Mon Sep 17 00:00:00 2001
From: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date: Sat, 17 Aug 2019 20:51:08 +0300
Subject: soc/intel: Use common romstage code
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This provides stack guards with checking and common
entry into postcar.

The code in cpu/intel/car/romstage.c is candidate
for becoming architectural so function prototype
is moved to <arch/romstage.h>.

Change-Id: I4c5a9789e7cf3f7f49a4a33e21dac894320a9639
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34893
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/northbridge/intel/pineview/memmap.c   | 1 -
 src/northbridge/intel/pineview/romstage.c | 2 +-
 2 files changed, 1 insertion(+), 2 deletions(-)

(limited to 'src/northbridge/intel/pineview')

diff --git a/src/northbridge/intel/pineview/memmap.c b/src/northbridge/intel/pineview/memmap.c
index eaf27f699f..9908f110cd 100644
--- a/src/northbridge/intel/pineview/memmap.c
+++ b/src/northbridge/intel/pineview/memmap.c
@@ -24,7 +24,6 @@
 #include <cbmem.h>
 #include <northbridge/intel/pineview/pineview.h>
 #include <cpu/x86/mtrr.h>
-#include <cpu/intel/romstage.h>
 #include <cpu/intel/smm_reloc.h>
 #include <stdint.h>
 #include <stage_cache.h>
diff --git a/src/northbridge/intel/pineview/romstage.c b/src/northbridge/intel/pineview/romstage.c
index e184f789d0..e60738ced5 100644
--- a/src/northbridge/intel/pineview/romstage.c
+++ b/src/northbridge/intel/pineview/romstage.c
@@ -26,7 +26,7 @@
 #include <southbridge/intel/i82801gx/i82801gx.h>
 #include <southbridge/intel/common/gpio.h>
 #include <southbridge/intel/common/pmclib.h>
-#include <cpu/intel/romstage.h>
+#include <arch/romstage.h>
 #include <cpu/x86/lapic.h>
 #include "raminit.h"
 #include "pineview.h"
-- 
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