From 7ee1c47cbaccadbba72a9207ad9089792b0e6964 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 26 Mar 2021 18:33:31 +0100 Subject: nb/intel/pineview: Correct HICLKGTCTL write Reference code uses the `0x06` as an or-mask, which makes more sense. Change-Id: I04e5262d9ab36ae866fccd90255e4a0f85328e85 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/51859 Reviewed-by: Patrick Rudolph Tested-by: build bot (Jenkins) --- src/northbridge/intel/pineview/raminit.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/northbridge/intel/pineview') diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c index 965adaef2f..680f3c901b 100644 --- a/src/northbridge/intel/pineview/raminit.c +++ b/src/northbridge/intel/pineview/raminit.c @@ -2320,7 +2320,7 @@ static void sdram_powersettings(struct sysinfo *s) MCHBAR8_AND(CISDCTRL + 3, ~0x80); MCHBAR16_AND(CICGDIS, ~0x1fff); MCHBAR32_AND(SBCLKGATECTRL, ~0x0001ffff); - MCHBAR16_AND(HICLKGTCTL, ~0x03ff & 0x06); + MCHBAR16_AND_OR(HICLKGTCTL, ~0x03ff, 0x06); MCHBAR32_AND_OR(HTCLKGTCTL, ~0xffffffff, 0x20); MCHBAR8_AND(TSMISC, ~1); MCHBAR8(C0WRDPYN) = s->selected_timings.CAS - 1 + 0x15; -- cgit v1.2.3