From 157b189f6b97b6e9ecd8d29edbbd045fbbc231f5 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Fri, 16 Aug 2019 14:02:25 +0300 Subject: cpu/intel: Enter romstage without BIST MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When entry to romstage is via cpu/intel/car/romstage.c BIST has not been passed down the path for sometime. Change-Id: I345975c53014902269cee21fc393331d33a84dce Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34908 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/northbridge/intel/pineview/romstage.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) (limited to 'src/northbridge/intel/pineview') diff --git a/src/northbridge/intel/pineview/romstage.c b/src/northbridge/intel/pineview/romstage.c index 8d7de45149..e184f789d0 100644 --- a/src/northbridge/intel/pineview/romstage.c +++ b/src/northbridge/intel/pineview/romstage.c @@ -27,7 +27,6 @@ #include #include #include -#include #include #include "raminit.h" #include "pineview.h" @@ -48,14 +47,13 @@ __weak void mb_pirq_setup(void) #define LPC_DEV PCI_DEV(0x0, 0x1f, 0x0) -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { u8 spd_addrmap[4] = {}; int boot_path, cbmem_was_initted; int s3resume = 0; - if (bist == 0) - enable_lapic(); + enable_lapic(); /* Enable GPIOs */ pci_write_config32(LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); @@ -63,9 +61,6 @@ void mainboard_romstage_entry(unsigned long bist) setup_pch_gpios(&mainboard_gpio_map); - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - enable_smbus(); /* Perform some early chipset initialization required -- cgit v1.2.3