From 0a760cd05b55755510a5672af3a1712a34a7e3aa Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Wed, 22 Jul 2020 11:43:10 +0200 Subject: nb/intel/pineview/hostbridge_regs.h: Clean up registers Sort them by ascending offsets. Tested with BUILD_TIMELESS=1, Foxconn D41S does not change. Change-Id: I521aa3e49b17a9fb6b279ae758801356e510d054 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/43725 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/northbridge/intel/pineview/hostbridge_regs.h | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'src/northbridge/intel/pineview') diff --git a/src/northbridge/intel/pineview/hostbridge_regs.h b/src/northbridge/intel/pineview/hostbridge_regs.h index b320b9e10f..506efcfbdd 100644 --- a/src/northbridge/intel/pineview/hostbridge_regs.h +++ b/src/northbridge/intel/pineview/hostbridge_regs.h @@ -5,9 +5,6 @@ #define EPBAR 0x40 #define MCHBAR 0x48 -#define PCIEXBAR 0x60 -#define DMIBAR 0x68 -#define PMIOBAR 0x78 #define GGC 0x52 /* GMCH Graphics Control */ @@ -21,6 +18,10 @@ #define BOARD_DEVEN (DEVEN_D0F0 | DEVEN_D2F0 | DEVEN_D2F1) #endif /* BOARD_DEVEN */ +#define PCIEXBAR 0x60 +#define DMIBAR 0x68 +#define PMIOBAR 0x78 + #define PAM0 0x90 #define PAM1 0x91 #define PAM2 0x92 -- cgit v1.2.3