From de6bda63d9890ac88a01368314fcf0802a694cf4 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 10 Apr 2018 13:40:39 +0200 Subject: nb/intel/pineview: Use common code for SMM in TSEG This also caches the TSEG region and therefore increases MTRR usage a little in some cases. Change-Id: I5f947cfae730b67bc76a581bc90cb10e5a2a4a52 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/25598 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/northbridge/intel/pineview/ram_calc.c | 48 +++++++++++++++++++++++++------ 1 file changed, 40 insertions(+), 8 deletions(-) (limited to 'src/northbridge/intel/pineview/ram_calc.c') diff --git a/src/northbridge/intel/pineview/ram_calc.c b/src/northbridge/intel/pineview/ram_calc.c index 62855c292e..21b926bc9a 100644 --- a/src/northbridge/intel/pineview/ram_calc.c +++ b/src/northbridge/intel/pineview/ram_calc.c @@ -24,6 +24,7 @@ #include #include #include +#include u8 decode_pciebar(u32 *const base, u32 *const len) { @@ -94,15 +95,46 @@ u32 decode_igd_gtt_size(const u32 gsm) return (u32)(gsmsize[gsm] << 10); } +/** Decodes used TSEG size to bytes. */ +static u32 decode_tseg_size(const u32 esmramc) +{ + if (!(esmramc & 1)) + return 0; + + switch ((esmramc >> 1) & 3) { + case 0: + return 1 << 20; + case 1: + return 2 << 20; + case 2: + return 8 << 20; + case 3: + default: + die("Bad TSEG setting.\n"); + } +} + +u32 northbridge_get_tseg_size(void) +{ + const u8 esmramc = pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC); + return decode_tseg_size(esmramc); +} + +u32 northbridge_get_tseg_base(void) +{ + return pci_read_config32(PCI_DEV(0, 0, 0), TSEG); +} + + /* Depending of UMA and TSEG configuration, TSEG might start at any * 1 MiB alignment. As this may cause very greedy MTRR setup, push * CBMEM top downwards to 4 MiB boundary. */ void *cbmem_top(void) { - uintptr_t top_of_ram = pci_read_config32(PCI_DEV(0, 0, 0), TSEG); - top_of_ram = ALIGN_DOWN(top_of_ram, 4*MiB); + uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); return (void *) top_of_ram; + } #define ROMSTAGE_RAM_STACK_SIZE 0x5000 @@ -124,14 +156,14 @@ void platform_enter_postcar(void) /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); - /* Cache two separate 4 MiB regions below the top of ram, this - * satisfies MTRR alignment requirements. If you modify this to - * cover TSEG, make sure UMA region is not set with WRBACK as it - * causes hard-to-recover boot failures. + /* Cache 8 MiB region below the top of ram and 2 MiB above top of + * ram to cover both cbmem as the TSEG region. */ top_of_ram = (uintptr_t)cbmem_top(); - postcar_frame_add_mtrr(&pcf, top_of_ram - 4*MiB, 4*MiB, MTRR_TYPE_WRBACK); - postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 4*MiB, MTRR_TYPE_WRBACK); + postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, + MTRR_TYPE_WRBACK); + postcar_frame_add_mtrr(&pcf, northbridge_get_tseg_base(), + northbridge_get_tseg_size(), MTRR_TYPE_WRBACK); run_postcar_phase(&pcf); -- cgit v1.2.3