From 62477931c88c701617445a3a23769583e7b830b5 Mon Sep 17 00:00:00 2001 From: Damien Zammit Date: Sun, 3 May 2015 21:34:38 +1000 Subject: northbridge/intel/pineview: Add minimal Pineview northbridge Based on i945. Tested on Intel D510MO mainboard, board boots to UART console with this code. Change-Id: I1d92a1aa6d6d767bda8379807dc26b50b9de75c9 Signed-off-by: Damien Zammit Reviewed-on: http://review.coreboot.org/10073 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc --- src/northbridge/intel/pineview/ram_calc.c | 58 +++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 src/northbridge/intel/pineview/ram_calc.c (limited to 'src/northbridge/intel/pineview/ram_calc.c') diff --git a/src/northbridge/intel/pineview/ram_calc.c b/src/northbridge/intel/pineview/ram_calc.c new file mode 100644 index 0000000000..e9f8eedb43 --- /dev/null +++ b/src/northbridge/intel/pineview/ram_calc.c @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Damien Zammit + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Use simple device model for this file even in ramstage */ +#define __SIMPLE_DEVICE__ + +#include +#include +#include + +static void *find_ramtop(void) +{ + uint32_t tom; + + if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1)) { + /* IGD enabled, get top of Memory from BSM register */ + tom = pci_read_config32(PCI_DEV(0,2,0), BSM); + } else + tom = (pci_read_config8(PCI_DEV(0,0,0), TOLUD) & 0xf7) << 24; + + /* if TSEG enabled subtract size */ + switch(pci_read_config8(PCI_DEV(0, 0, 0), ESMRAM) & 0x07) { + case 0x01: + /* 1MB TSEG */ + tom -= 0x100000; + break; + case 0x03: + /* 2MB TSEG */ + tom -= 0x200000; + break; + case 0x05: + /* 8MB TSEG */ + tom -= 0x800000; + break; + default: + /* TSEG either disabled or invalid */ + break; + } + return (void *)tom; +} + +void *cbmem_top(void) +{ + return find_ramtop(); +} -- cgit v1.2.3