From a8a9f34e9b7be8781c06c9d6fcc39f52bf31bd23 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sun, 24 Dec 2017 08:11:13 +0100 Subject: sb/intel/i82801{g,j}x: Automatically generate ACPI PIRQ tables Both southbridges need to be done at once since this southbridge code is used for different northbridges, which fails to compile when done separately. This needs an acpi_name functions in the northbridge code to be defined. TESTED on Intel DG43GT: show correct PIRQ ACPI entries in /sys/firmware/acpi/tables/SSDT. Change-Id: I286d251ddf8fcae27dd07011a1cd62d8f4847683 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/22981 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/northbridge/intel/pineview/northbridge.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'src/northbridge/intel/pineview/northbridge.c') diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c index 93c7558931..0bba03da29 100644 --- a/src/northbridge/intel/pineview/northbridge.c +++ b/src/northbridge/intel/pineview/northbridge.c @@ -147,12 +147,29 @@ static void mch_domain_init(struct device *dev) pci_write_config32(dev, PCI_COMMAND, reg32); } +static const char *northbridge_acpi_name(const struct device *dev) +{ + if (dev->path.type == DEVICE_PATH_DOMAIN) + return "PCI0"; + + if (dev->path.type != DEVICE_PATH_PCI || dev->bus->secondary != 0) + return NULL; + + switch (dev->path.pci.devfn) { + case PCI_DEVFN(0, 0): + return "MCHC"; + } + + return NULL; +} + static struct device_operations pci_domain_ops = { .read_resources = mch_domain_read_resources, .set_resources = mch_domain_set_resources, .init = mch_domain_init, .scan_bus = pci_domain_scan_bus, .acpi_fill_ssdt_generator = generate_cpu_entries, + .acpi_name = northbridge_acpi_name, }; static void cpu_bus_init(struct device *dev) -- cgit v1.2.3