From 5ac723e5a4a22bc9a08098cd59de5026b18d362d Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 29 Apr 2020 09:09:12 +0200 Subject: nb/intel: Fix 16-bit read/write PCI_COMMAND register Change-Id: I7c7fb10308a6fcd1ead292c53ed03ddc693f6f15 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/40835 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/northbridge/intel/pineview/northbridge.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) (limited to 'src/northbridge/intel/pineview/northbridge.c') diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c index 83bc60eece..856eab3301 100644 --- a/src/northbridge/intel/pineview/northbridge.c +++ b/src/northbridge/intel/pineview/northbridge.c @@ -147,12 +147,8 @@ static void mch_domain_set_resources(struct device *dev) static void mch_domain_init(struct device *dev) { - u32 reg32; - /* Enable SERR */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_SERR; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR); } static const char *northbridge_acpi_name(const struct device *dev) -- cgit v1.2.3