From 51fdb9256a56c95dbab9b0542eb84df79a640e34 Mon Sep 17 00:00:00 2001 From: Damien Zammit Date: Mon, 18 Jan 2016 18:34:52 +1100 Subject: nb/intel/pineview: Native VGA init (CRT) VGA grub console works but display wobbles left/right drm/i915 driver reports one error: - [drm:i915_irq_handler] *ERROR* pipe A underrun - Monitor does not display 1920x1080 after modeset - Other resolutions look out of sync Cause: suspect single bug in raminit (chipset init) Change-Id: I2dcf59f8f30efe98f17a937bf98f5ab7221fc3ac Signed-off-by: Damien Zammit Reviewed-on: https://review.coreboot.org/12921 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/northbridge/intel/pineview/northbridge.c | 121 +++++++++++---------------- 1 file changed, 48 insertions(+), 73 deletions(-) (limited to 'src/northbridge/intel/pineview/northbridge.c') diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c index 0f534dc163..6a3e829f1b 100644 --- a/src/northbridge/intel/pineview/northbridge.c +++ b/src/northbridge/intel/pineview/northbridge.c @@ -29,18 +29,40 @@ #include #include -/* Reserve segments A and B: +/* Reserve everything between A segment and 1MB: * * 0xa0000 - 0xbffff: legacy VGA + * 0xc0000 - 0xcffff: VGA OPROM (needed by kernel) + * 0xe0000 - 0xfffff: SeaBIOS, if used, otherwise DMI */ static const int legacy_hole_base_k = 0xa0000 / 1024; static const int legacy_hole_size_k = 128; +static void add_fixed_resources(device_t dev, int index) +{ + struct resource *resource; + + resource = new_resource(dev, index++); + resource->base = (resource_t) 0xfed00000; + resource->size = (resource_t) 0x00100000; + resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + + mmio_resource(dev, index++, legacy_hole_base_k, + (0xc0000 >> 10) - legacy_hole_base_k); + reserved_ram_resource(dev, index++, 0xc0000 >> 10, + (0x100000 - 0xc0000) >> 10); +} + static void mch_domain_read_resources(device_t dev) { u64 tom, touud; - u32 tomk, tolud, uma_sizek = 0, usable_tomk; + u32 tomk, tolud, tseg_sizek; u32 pcie_config_base, pcie_config_size; + u16 index; + const u32 top32memk = 4 * (GiB / KiB); + + index = 3; pci_domain_read_resources(dev); @@ -56,15 +78,13 @@ static void mch_domain_read_resources(device_t dev) tom = pci_read_config16(dev, TOM) & 0x1ff; tom <<= 27; - printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx\n", + printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx ", touud, tolud, tom); tomk = tolud >> 10; - /* Graphics memory comes next */ - const u16 ggc = pci_read_config16(dev, GGC); - /* Graphics memory */ + const u16 ggc = pci_read_config16(dev, GGC); const u32 gms_sizek = decode_igd_memory_size((ggc >> 4) & 0xf); printk(BIOS_DEBUG, "%uM UMA", gms_sizek >> 10); tomk -= gms_sizek; @@ -74,59 +94,50 @@ static void mch_domain_read_resources(device_t dev) printk(BIOS_DEBUG, " and %uM GTT\n", gsm_sizek >> 10); tomk -= gsm_sizek; - uma_sizek = gms_sizek + gsm_sizek; - - usable_tomk = ALIGN_DOWN(tomk, 64 << 10); - if (tomk - usable_tomk > (16 << 10)) - usable_tomk = tomk; + const u32 tseg_basek = pci_read_config32(dev, TSEG) >> 10; + const u32 igd_basek = pci_read_config32(dev, GBSM) >> 10; + const u32 gtt_basek = pci_read_config32(dev, BGSM) >> 10; - printk(BIOS_INFO, "Available memory below 4GB: %uM\n", usable_tomk >> 10); + /* Subtract TSEG size */ + tseg_sizek = gtt_basek - tseg_basek; + tomk -= tseg_sizek; /* Report the memory regions */ - ram_resource(dev, 3, 0, legacy_hole_base_k); - ram_resource(dev, 4, legacy_hole_base_k + legacy_hole_size_k, - (usable_tomk - (legacy_hole_base_k + legacy_hole_size_k))); - - mmio_resource(dev, 5, legacy_hole_base_k, - (0xc0000 >> 10) - legacy_hole_base_k); + ram_resource(dev, index++, 0, 640); + ram_resource(dev, index++, 768, tomk - 768); + reserved_ram_resource(dev, index++, tseg_basek, tseg_sizek); + reserved_ram_resource(dev, index++, gtt_basek, gsm_sizek); + reserved_ram_resource(dev, index++, igd_basek, gms_sizek); /* - * If >= 4GB installed then memory from TOLUD to 4GB + * If > 4GB installed then memory from TOLUD to 4GB * is remapped above TOM, TOUUD will account for both */ touud >>= 10; /* Convert to KB */ - if (touud > 4096 * 1024) { - ram_resource(dev, 6, 4096 * 1024, touud - (4096 * 1024)); + if (touud > top32memk) { + ram_resource(dev, index++, top32memk, touud - top32memk); printk(BIOS_INFO, "Available memory above 4GB: %lluM\n", - (touud >> 10) - 4096); + (touud - top32memk) >> 10); } - printk(BIOS_DEBUG, "Adding UMA memory area base=0x%llx " - "size=0x%llx\n", ((u64)tomk) << 10, ((u64)uma_sizek) << 10); - /* Don't use uma_resource() as our UMA touches the PCI hole. */ - fixed_mem_resource(dev, 7, tomk, uma_sizek, IORESOURCE_RESERVE); - if (decode_pciebar(&pcie_config_base, &pcie_config_size)) { printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x " - "size=0x%x\n", pcie_config_base, pcie_config_size); - fixed_mem_resource(dev, 8, pcie_config_base >> 10, + "size=0x%x\n", pcie_config_base, pcie_config_size); + fixed_mem_resource(dev, index++, pcie_config_base >> 10, pcie_config_size >> 10, IORESOURCE_RESERVE); } + add_fixed_resources(dev, index); + set_top_of_ram(tomk << 10); } static void mch_domain_set_resources(device_t dev) { - struct resource *resource; - int i; + struct resource *res; - for (i = 3; i < 9; ++i) { - /* Report read resources. */ - resource = probe_resource(dev, i); - if (resource) - report_resource_stored(dev, resource, ""); - } + for (res = dev->resource_list; res; res = res->next) + report_resource_stored(dev, res, ""); assign_resources(dev->link_list); } @@ -144,7 +155,6 @@ static void mch_domain_init(device_t dev) static struct device_operations pci_domain_ops = { .read_resources = mch_domain_read_resources, .set_resources = mch_domain_set_resources, - .enable_resources = NULL, .init = mch_domain_init, .scan_bus = pci_domain_scan_bus, .ops_pci_bus = pci_bus_default_ops, @@ -160,7 +170,6 @@ static struct device_operations cpu_bus_ops = { .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, .init = cpu_bus_init, - .scan_bus = 0, }; @@ -190,41 +199,7 @@ static void enable_dev(device_t dev) } } -static void pineview_init(void *const chip_info) -{ - int dev, fn; - - struct device *const d0f0 = dev_find_slot(0, 0); - - const struct { - u8 fn; - u8 bitbase; - } intfunc[] = { - {0, 0}, - {0, 1}, /* PEG */ - {1, 3}, /* IGD */ - {3, 6}, /* ME */ - }; - - /* Hide internal functions based on devicetree info. */ - for (dev = 3; dev > 0; --dev) { - for (fn = intfunc[dev].fn; fn >= 0; --fn) { - const struct device *const d = - dev_find_slot(0, PCI_DEVFN(dev, fn)); - if (!d || d->enabled) continue; - const u32 deven = pci_read_config32(d0f0, DEVEN); - pci_write_config32(d0f0, DEVEN, deven - & ~(1 << (intfunc[dev].bitbase + fn))); - } - } - - const u32 deven = pci_read_config32(d0f0, DEVEN); - if (!(deven & (0xf << 6))) - pci_write_config32(d0f0, DEVEN, deven & ~(1 << 14)); -} - struct chip_operations northbridge_intel_pineview_ops = { CHIP_NAME("Intel Pineview Northbridge") .enable_dev = enable_dev, - .init = pineview_init, }; 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