From 62477931c88c701617445a3a23769583e7b830b5 Mon Sep 17 00:00:00 2001 From: Damien Zammit Date: Sun, 3 May 2015 21:34:38 +1000 Subject: northbridge/intel/pineview: Add minimal Pineview northbridge Based on i945. Tested on Intel D510MO mainboard, board boots to UART console with this code. Change-Id: I1d92a1aa6d6d767bda8379807dc26b50b9de75c9 Signed-off-by: Damien Zammit Reviewed-on: http://review.coreboot.org/10073 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc --- src/northbridge/intel/pineview/iomap.h | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 src/northbridge/intel/pineview/iomap.h (limited to 'src/northbridge/intel/pineview/iomap.h') diff --git a/src/northbridge/intel/pineview/iomap.h b/src/northbridge/intel/pineview/iomap.h new file mode 100644 index 0000000000..6cced82949 --- /dev/null +++ b/src/northbridge/intel/pineview/iomap.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Damien Zammit + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef PINEVIEW_IOMAP_H +#define PINEVIEW_IOMAP_H + +/* 4 KB per PCIe device */ +#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS + +#define DEFAULT_MCHBAR 0xfed14000 /* 16 KB */ +#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ +#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ + +#endif /* PINEVIEW_IOMAP_H */ -- cgit v1.2.3