From e6c8f7ec200e72c76eb2ff73720acff9c88e73c8 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Thu, 9 Aug 2018 11:31:51 +0200 Subject: nb/intel/*/gma.c: Skip NGI when VGA decode is not enabled Writes to VGA MEM and IO by NGI are invalid if the IGD is not decoding them. Change-Id: I4b9329d14105eb563a0d4aea6ef75ff11febf6df Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/27984 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Felix Held --- src/northbridge/intel/pineview/gma.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) (limited to 'src/northbridge/intel/pineview/gma.c') diff --git a/src/northbridge/intel/pineview/gma.c b/src/northbridge/intel/pineview/gma.c index 8cf4d22554..02100e908d 100644 --- a/src/northbridge/intel/pineview/gma.c +++ b/src/northbridge/intel/pineview/gma.c @@ -275,6 +275,8 @@ static void gma_func0_init(struct device *dev) struct resource *pio_res; struct northbridge_intel_pineview_config *conf = dev->chip_info; + int vga_disable = (pci_read_config16(dev, GGC) & 2) >> 1; + /* Find base addresses */ mmio_res = find_resource(dev, 0x10); gtt_res = find_resource(dev, 0x1c); @@ -282,11 +284,17 @@ static void gma_func0_init(struct device *dev) physbase = pci_read_config32(dev, 0x5c) & ~0xf; if (gtt_res && gtt_res->base && physbase && pio_res && pio_res->base) { - printk(BIOS_SPEW, "Initializing VGA. MMIO 0x%llx\n", - mmio_res->base); - intel_gma_init(conf, dev, res2mmio(mmio_res, 0, 0), - res2mmio(gtt_res, 0, 0), - physbase, pio_res->base); + if (vga_disable) { + printk(BIOS_INFO, + "IGD is not decoding legacy VGA MEM and IO: skipping NATIVE graphic init\n"); + } else { + printk(BIOS_SPEW, "Initializing VGA. MMIO 0x%llx\n", + mmio_res->base); + intel_gma_init(conf, dev, + res2mmio(mmio_res, 0, 0), + res2mmio(gtt_res, 0, 0), + physbase, pio_res->base); + } } /* Linux relies on VBT for panel info. */ -- cgit v1.2.3