From 39ff703aa989ebdc056dd27e181fd135a551f522 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 9 Mar 2020 21:39:44 +0100 Subject: nb/intel/pineview: Clean up code and comments - Reformat some lines of code - Put names to all MCHBAR registers in a separate file - Rewrite several comments - Use C-style comments for consistency - Rewrite some hex constants - Use HOST_BRIDGE instead of PCI_DEV(0, 0, 0) - Align a bunch of things Tested with BUILD_TIMELESS=1, foxconn/d41s remains unaffected. Change-Id: I29104b0c24d66c6f49844f99d62ec433bb31bdaf Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39414 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/northbridge/intel/pineview/gma.c | 111 +++++++++++++++-------------------- 1 file changed, 48 insertions(+), 63 deletions(-) (limited to 'src/northbridge/intel/pineview/gma.c') diff --git a/src/northbridge/intel/pineview/gma.c b/src/northbridge/intel/pineview/gma.c index dd6cb32596..db2bb825b7 100644 --- a/src/northbridge/intel/pineview/gma.c +++ b/src/northbridge/intel/pineview/gma.c @@ -36,7 +36,7 @@ #include "chip.h" #include "pineview.h" -#define GTTSIZE (512*1024) +#define GTTSIZE (512 * 1024) #define PGETBL2_CTL 0x20c4 #define PGETBL2_1MB (1 << 8) @@ -54,7 +54,7 @@ ADPA_CRT_HOTPLUG_VOLREF_325MV | \ ADPA_CRT_HOTPLUG_ENABLE) -static struct resource *gtt_res = NULL; +static struct resource *gtt_res = NULL; static struct resource *mmio_res = NULL; uintptr_t gma_get_gnvs_aslb(const void *gnvs) @@ -126,8 +126,7 @@ static void intel_gma_init(const struct northbridge_intel_pineview_config *info, | ADPA_USE_VGA_HVPOLARITY | ADPA_VSYNC_CNTL_ENABLE | ADPA_HSYNC_CNTL_ENABLE - | ADPA_DPMS_ON - ); + | ADPA_DPMS_ON); write32(mmio + 0x7041c, 0x0); @@ -137,14 +136,16 @@ static void intel_gma_init(const struct northbridge_intel_pineview_config *info, write32(mmio + PIPESRC(1), 0x027f01df); vga_misc_write(0x67); - const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, - 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, - 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, - 0xff + const u8 cr[25] = { + 0x5f, 0x4f, 0x50, 0x82, 0x55, + 0x81, 0xbf, 0x1f, 0x00, 0x4f, + 0x0d, 0x0e, 0x00, 0x00, 0x00, + 0x00, 0x9c, 0x8e, 0x8f, 0x28, + 0x1f, 0x96, 0xb9, 0xa3, 0xff, }; vga_cr_write(0x11, 0); - for (i = 0; i <= 0x18; i++) + for (i = 0; i < ARRAY_SIZE(cr); i++) vga_cr_write(i, cr[i]); // Disable screen memory to prevent garbage from appearing. @@ -157,15 +158,14 @@ static void intel_gma_init(const struct northbridge_intel_pineview_config *info, DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL | DPLL_VGA_MODE_DIS | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 - | 0x400601 - ); + | 0x400601); + mdelay(1); write32(mmio + DPLL(0), DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL | DPLL_VGA_MODE_DIS | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 - | 0x400601 - ); + | 0x400601); write32(mmio + ADPA, ADPA_DAC_ENABLE | ADPA_PIPE_A_SELECT @@ -173,8 +173,7 @@ static void intel_gma_init(const struct northbridge_intel_pineview_config *info, | ADPA_USE_VGA_HVPOLARITY | ADPA_VSYNC_CNTL_ENABLE | ADPA_HSYNC_CNTL_ENABLE - | ADPA_DPMS_ON - ); + | ADPA_DPMS_ON); write32(mmio + HTOTAL(1), 0x031f027f); write32(mmio + HBLANK(1), 0x03170287); @@ -183,23 +182,12 @@ static void intel_gma_init(const struct northbridge_intel_pineview_config *info, write32(mmio + VBLANK(1), 0x020401e7); write32(mmio + VSYNC(1), 0x01eb01e9); - write32(mmio + HTOTAL(0), - ((hactive - 1) << 16) - | (hactive - 1)); - write32(mmio + HBLANK(0), - ((hactive - 1) << 16) - | (hactive - 1)); - write32(mmio + HSYNC(0), - ((hactive - 1) << 16) - | (hactive - 1)); - - write32(mmio + VTOTAL(0), ((vactive - 1) << 16) - | (vactive - 1)); - write32(mmio + VBLANK(0), ((vactive - 1) << 16) - | (vactive - 1)); - write32(mmio + VSYNC(0), - ((vactive - 1) << 16) - | (vactive - 1)); + write32(mmio + HTOTAL(0), ((hactive - 1) << 16) | (hactive - 1)); + write32(mmio + HBLANK(0), ((hactive - 1) << 16) | (hactive - 1)); + write32(mmio + HSYNC(0), ((hactive - 1) << 16) | (hactive - 1)); + write32(mmio + VTOTAL(0), ((vactive - 1) << 16) | (vactive - 1)); + write32(mmio + VBLANK(0), ((vactive - 1) << 16) | (vactive - 1)); + write32(mmio + VSYNC(0), ((vactive - 1) << 16) | (vactive - 1)); write32(mmio + PF_WIN_POS(0), 0); @@ -228,8 +216,7 @@ static void intel_gma_init(const struct northbridge_intel_pineview_config *info, | ADPA_USE_VGA_HVPOLARITY | ADPA_VSYNC_CNTL_ENABLE | ADPA_HSYNC_CNTL_ENABLE - | ADPA_DPMS_ON - ); + | ADPA_DPMS_ON); write32(mmio + DSPFW3, 0x7f3f00c1); write32(mmio + MI_MODE, 0x200 | VS_TIMER_DISPATCH); @@ -246,16 +233,16 @@ static void intel_gma_init(const struct northbridge_intel_pineview_config *info, temp = read32(mmio + PGETBL2_CTL); printk(BIOS_INFO, "GTT PGETBL2_CTL register: 0x%08x\n", temp); - /* Clear interrupts. */ - write32(mmio + DEIIR, 0xffffffff); + /* Clear interrupts */ + write32(mmio + DEIIR, 0xffffffff); write32(mmio + SDEIIR, 0xffffffff); - write32(mmio + IIR, 0xffffffff); - write32(mmio + IMR, 0xffffffff); - write32(mmio + EIR, 0xffffffff); + write32(mmio + IIR, 0xffffffff); + write32(mmio + IMR, 0xffffffff); + write32(mmio + EIR, 0xffffffff); vga_textmode_init(); - /* Enable screen memory. */ + /* Enable screen memory */ vga_sr_write(1, vga_sr_read(1) & ~0x20); } @@ -269,7 +256,7 @@ static void gma_func0_init(struct device *dev) pci_write_config32(dev, PCI_COMMAND, reg32); if (!CONFIG(MAINBOARD_DO_NATIVE_VGA_INIT)) { - /* PCI Init, will run VBIOS */ + /* PCI init, will run VBIOS */ pci_dev_init(dev); } else { u32 physbase; @@ -280,14 +267,14 @@ static void gma_func0_init(struct device *dev) /* Find base addresses */ mmio_res = find_resource(dev, 0x10); - gtt_res = find_resource(dev, 0x1c); - pio_res = find_resource(dev, 0x14); + gtt_res = find_resource(dev, 0x1c); + pio_res = find_resource(dev, 0x14); physbase = pci_read_config32(dev, 0x5c) & ~0xf; if (gtt_res && gtt_res->base && physbase && pio_res && pio_res->base) { if (vga_disable) { - printk(BIOS_INFO, - "IGD is not decoding legacy VGA MEM and IO: skipping NATIVE graphic init\n"); + printk(BIOS_INFO, "IGD is not decoding legacy VGA MEM and IO: " + "skipping NATIVE graphic init\n"); } else { printk(BIOS_SPEW, "Initializing VGA. MMIO 0x%llx\n", mmio_res->base); @@ -307,7 +294,7 @@ static void gma_func0_init(struct device *dev) const struct i915_gpu_controller_info *intel_gma_get_controller_info(void) { - struct device *dev = pcidev_on_root(0x2, 0); + struct device *dev = pcidev_on_root(2, 0); if (!dev) { printk(BIOS_WARNING, "WARNING: Can't find IGD (0,2,0)\n"); return NULL; @@ -316,10 +303,8 @@ const struct i915_gpu_controller_info *intel_gma_get_controller_info(void) return &chip->gfx; } -static unsigned long -gma_write_acpi_tables(struct device *const dev, - unsigned long current, - struct acpi_rsdp *const rsdp) +static unsigned long gma_write_acpi_tables(struct device *const dev, unsigned long current, + struct acpi_rsdp *const rsdp) { igd_opregion_t *opregion = (igd_opregion_t *)current; global_nvs_t *gnvs; @@ -352,25 +337,25 @@ static struct pci_operations gma_pci_ops = { }; static struct device_operations gma_func0_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .acpi_fill_ssdt_generator = 0, - .init = gma_func0_init, - .scan_bus = 0, - .enable = 0, - .ops_pci = &gma_pci_ops, - .acpi_name = gma_acpi_name, - .write_acpi_tables = gma_write_acpi_tables, + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .acpi_fill_ssdt_generator = NULL, + .init = gma_func0_init, + .scan_bus = NULL, + .enable = NULL, + .ops_pci = &gma_pci_ops, + .acpi_name = gma_acpi_name, + .write_acpi_tables = gma_write_acpi_tables, }; static const unsigned short pci_device_ids[] = { - 0xa001, 0 + 0xa001, 0, }; static const struct pci_driver gma __pci_driver = { - .ops = &gma_func0_ops, - .vendor = PCI_VENDOR_ID_INTEL, + .ops = &gma_func0_ops, + .vendor = PCI_VENDOR_ID_INTEL, .devices = pci_device_ids, }; -- cgit v1.2.3