From 1318ab475ddcae5fdd8f41b66c4d7034c8b3d396 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Wed, 20 Jan 2021 13:31:09 +0100 Subject: nb/intel/pineview: Define and use MMCONF_BUS_NUMBER Note that bootblock.c originally wrote a reserved bit of the PCIEXBAR register. The `length` bitfield was set to 0, so assume 256 busses. Change-Id: Ie967747b4bf559b5aedc67cbcd35bca51f5a692e Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/49760 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/northbridge/intel/pineview/bootblock.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) (limited to 'src/northbridge/intel/pineview/bootblock.c') diff --git a/src/northbridge/intel/pineview/bootblock.c b/src/northbridge/intel/pineview/bootblock.c index 7fb506e751..61bd2eedcd 100644 --- a/src/northbridge/intel/pineview/bootblock.c +++ b/src/northbridge/intel/pineview/bootblock.c @@ -1,14 +1,23 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include +#include #include "pineview.h" -#define MMCONF_256_BUSSES 16 -#define ENABLE 1 +static uint32_t encode_pciexbar_length(void) +{ + switch (CONFIG_MMCONF_BUS_NUMBER) { + case 256: return 0 << 1; + case 128: return 1 << 1; + case 64: return 2 << 1; + default: return dead_code_t(uint32_t); + } +} void bootblock_early_northbridge_init(void) { - pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, - CONFIG_MMCONF_BASE_ADDRESS | MMCONF_256_BUSSES | ENABLE); + const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; + pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg32); } -- cgit v1.2.3