From f7060f1d0f72bab5b349846bc97784895643cf50 Mon Sep 17 00:00:00 2001 From: Damien Zammit Date: Sat, 14 Nov 2015 00:59:21 +1100 Subject: northbridge/intel/pineview: Add remaining boilerplate code for northbridge This patch does *not* include native raminit Change-Id: I3fb8146ef7fe2ad27c167ecd2fb0fd629f051cc1 Signed-off-by: Damien Zammit Reviewed-on: https://review.coreboot.org/12430 Reviewed-by: Alexandru Gagniuc Tested-by: build bot (Jenkins) --- src/northbridge/intel/pineview/acpi.c | 34 +++------------------------------- 1 file changed, 3 insertions(+), 31 deletions(-) (limited to 'src/northbridge/intel/pineview/acpi.c') diff --git a/src/northbridge/intel/pineview/acpi.c b/src/northbridge/intel/pineview/acpi.c index f29d235b20..9dd8e311be 100644 --- a/src/northbridge/intel/pineview/acpi.c +++ b/src/northbridge/intel/pineview/acpi.c @@ -24,42 +24,14 @@ unsigned long acpi_fill_mcfg(unsigned long current) { - device_t dev; + u32 length = 0; u32 pciexbar = 0; - u32 pciexbar_reg; - u32 reg32; int max_buses; - const struct { - u16 num_buses; - u32 addr_mask; - } busmask[] = { - {256, 0xff000000}, - {128, 0xf8000000}, - {64, 0xfc000000}, - {0, 0}, - }; - dev = dev_find_slot(0, PCI_DEVFN(0,0)); - if (!dev) + if (!decode_pciebar(&pciexbar, &length)) return current; - pciexbar_reg = pci_read_config32(dev, PCIEXBAR); - - // MMCFG not supported or not enabled. - if (!(pciexbar_reg & (1 << 0))) { - printk(BIOS_WARNING, "WARNING: MMCONF not set\n"); - return current; - } - - reg32 = (pciexbar_reg >> 1) & 3; - pciexbar = pciexbar_reg & busmask[reg32].addr_mask; - max_buses = busmask[reg32].num_buses; - - if (!pciexbar) { - printk(BIOS_WARNING, "WARNING: pciexbar invalid\n"); - return current; - } - + max_buses = length >> 20; current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, pciexbar, 0x0, 0x0, max_buses - 1); -- cgit v1.2.3