From 62477931c88c701617445a3a23769583e7b830b5 Mon Sep 17 00:00:00 2001 From: Damien Zammit Date: Sun, 3 May 2015 21:34:38 +1000 Subject: northbridge/intel/pineview: Add minimal Pineview northbridge Based on i945. Tested on Intel D510MO mainboard, board boots to UART console with this code. Change-Id: I1d92a1aa6d6d767bda8379807dc26b50b9de75c9 Signed-off-by: Damien Zammit Reviewed-on: http://review.coreboot.org/10073 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc --- src/northbridge/intel/pineview/acpi.c | 67 +++++++++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) create mode 100644 src/northbridge/intel/pineview/acpi.c (limited to 'src/northbridge/intel/pineview/acpi.c') diff --git a/src/northbridge/intel/pineview/acpi.c b/src/northbridge/intel/pineview/acpi.c new file mode 100644 index 0000000000..f29d235b20 --- /dev/null +++ b/src/northbridge/intel/pineview/acpi.c @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Damien Zammit + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + device_t dev; + u32 pciexbar = 0; + u32 pciexbar_reg; + u32 reg32; + int max_buses; + const struct { + u16 num_buses; + u32 addr_mask; + } busmask[] = { + {256, 0xff000000}, + {128, 0xf8000000}, + {64, 0xfc000000}, + {0, 0}, + }; + + dev = dev_find_slot(0, PCI_DEVFN(0,0)); + if (!dev) + return current; + + pciexbar_reg = pci_read_config32(dev, PCIEXBAR); + + // MMCFG not supported or not enabled. + if (!(pciexbar_reg & (1 << 0))) { + printk(BIOS_WARNING, "WARNING: MMCONF not set\n"); + return current; + } + + reg32 = (pciexbar_reg >> 1) & 3; + pciexbar = pciexbar_reg & busmask[reg32].addr_mask; + max_buses = busmask[reg32].num_buses; + + if (!pciexbar) { + printk(BIOS_WARNING, "WARNING: pciexbar invalid\n"); + return current; + } + + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, + pciexbar, 0x0, 0x0, max_buses - 1); + + return current; +} -- cgit v1.2.3