From 62477931c88c701617445a3a23769583e7b830b5 Mon Sep 17 00:00:00 2001 From: Damien Zammit Date: Sun, 3 May 2015 21:34:38 +1000 Subject: northbridge/intel/pineview: Add minimal Pineview northbridge Based on i945. Tested on Intel D510MO mainboard, board boots to UART console with this code. Change-Id: I1d92a1aa6d6d767bda8379807dc26b50b9de75c9 Signed-off-by: Damien Zammit Reviewed-on: http://review.coreboot.org/10073 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc --- src/northbridge/intel/pineview/Makefile.inc | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 src/northbridge/intel/pineview/Makefile.inc (limited to 'src/northbridge/intel/pineview/Makefile.inc') diff --git a/src/northbridge/intel/pineview/Makefile.inc b/src/northbridge/intel/pineview/Makefile.inc new file mode 100644 index 0000000000..9330b1787b --- /dev/null +++ b/src/northbridge/intel/pineview/Makefile.inc @@ -0,0 +1,24 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2007-2009 coresystems GmbH +# Copyright (C) 2015 Damien Zammit +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +ifeq ($(CONFIG_NORTHBRIDGE_INTEL_PINEVIEW),y) + +ramstage-y += ram_calc.c +ramstage-y += acpi.c + +romstage-y += ram_calc.c + +endif -- cgit v1.2.3