From 20f71369d95d9691e668455b2262c80997fc8c3f Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 10 Apr 2018 16:15:09 +0200 Subject: nb/intel/pineview: Put stage cache in TSEG TSEG is not accessible in ring 0 after it is locked in ramstage, in contrast with cbmem which remains accessible. Assuming SMM does not touch the cache this is a good region to cache stages. Tested on Foxconn D41S. Change-Id: I3d163e8ff328ba01425b524a673f34a96fb93ea7 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/25605 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/northbridge/intel/pineview/Makefile.inc | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/northbridge/intel/pineview/Makefile.inc') diff --git a/src/northbridge/intel/pineview/Makefile.inc b/src/northbridge/intel/pineview/Makefile.inc index 524bcae372..90a9f48373 100644 --- a/src/northbridge/intel/pineview/Makefile.inc +++ b/src/northbridge/intel/pineview/Makefile.inc @@ -27,5 +27,8 @@ romstage-y += raminit.c romstage-y += early_init.c postcar-y += ram_calc.c +romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c +ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c +postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c endif -- cgit v1.2.3