From 1318ab475ddcae5fdd8f41b66c4d7034c8b3d396 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Wed, 20 Jan 2021 13:31:09 +0100 Subject: nb/intel/pineview: Define and use MMCONF_BUS_NUMBER Note that bootblock.c originally wrote a reserved bit of the PCIEXBAR register. The `length` bitfield was set to 0, so assume 256 busses. Change-Id: Ie967747b4bf559b5aedc67cbcd35bca51f5a692e Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/49760 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/northbridge/intel/pineview/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/northbridge/intel/pineview/Kconfig') diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig index 535e8e2720..b1863ef901 100644 --- a/src/northbridge/intel/pineview/Kconfig +++ b/src/northbridge/intel/pineview/Kconfig @@ -23,6 +23,10 @@ config VGA_BIOS_ID config MMCONF_BASE_ADDRESS default 0xe0000000 +config MMCONF_BUS_NUMBER + int + default 256 + config SMM_RESERVED_SIZE hex default 0x80000 -- cgit v1.2.3