From d53fd704f252ffde35c8bf2f2b16260edce76e79 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Wed, 14 Aug 2019 06:25:55 +0300 Subject: intel/smm/gen1: Use smm_subregion() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I371ed41f485b3143e47f091681198d6674928897 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34740 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/northbridge/intel/nehalem/memmap.c | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) (limited to 'src/northbridge/intel/nehalem') diff --git a/src/northbridge/intel/nehalem/memmap.c b/src/northbridge/intel/nehalem/memmap.c index 1687ddf78b..fd10542832 100644 --- a/src/northbridge/intel/nehalem/memmap.c +++ b/src/northbridge/intel/nehalem/memmap.c @@ -21,8 +21,8 @@ #include #include #include +#include #include -#include #include #include "nehalem.h" @@ -33,12 +33,12 @@ static uintptr_t smm_region_start(void) return tom; } -u32 northbridge_get_tseg_base(void) +static uintptr_t northbridge_get_tseg_base(void) { - return (u32)smm_region_start(); + return smm_region_start(); } -u32 northbridge_get_tseg_size(void) +static size_t northbridge_get_tseg_size(void) { return CONFIG_SMM_TSEG_SIZE; } @@ -48,13 +48,10 @@ void *cbmem_top(void) return (void *) smm_region_start(); } -void stage_cache_external_region(void **base, size_t *size) +void smm_region(uintptr_t *start, size_t *size) { - /* The stage cache lives at the end of TSEG region. - * The top of RAM is defined to be the TSEG base address. */ - *size = CONFIG_SMM_RESERVED_SIZE; - *base = (void *)((uintptr_t)northbridge_get_tseg_base() + - northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE); + *start = northbridge_get_tseg_base(); + *size = northbridge_get_tseg_size(); } void fill_postcar_frame(struct postcar_frame *pcf) -- cgit v1.2.3