From 95de2317c6c6379e43d3b3c27d34eb66198dbe0a Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 17 Feb 2020 13:08:53 +0100 Subject: nb/intel/nehalem: Rename to ironlake The code is for Arrandale CPUs, whose System Agent is Ironlake. This change simply replaces `nehalem` with `ironlake` and `NEHALEM` with `IRONLAKE`. The remaining `Nehalem` cases are handled later, as changing some of them would impact the resulting binary. Tested with BUILD_TIMELESS=1 without adding the configuration options into the binary, and packardbell/ms2290 does not change. Change-Id: I8eb96eeb5e69f49150d47793b33e87b650c64acc Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/38941 Reviewed-by: Felix Held Reviewed-by: Martin Roth Tested-by: build bot (Jenkins) --- src/northbridge/intel/nehalem/acpi.c | 68 ------------------------------------ 1 file changed, 68 deletions(-) delete mode 100644 src/northbridge/intel/nehalem/acpi.c (limited to 'src/northbridge/intel/nehalem/acpi.c') diff --git a/src/northbridge/intel/nehalem/acpi.c b/src/northbridge/intel/nehalem/acpi.c deleted file mode 100644 index 43b13c286a..0000000000 --- a/src/northbridge/intel/nehalem/acpi.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2012 The Chromium OS Authors - * Copyright (C) 2013 Vladimir Serbinenko - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define __SIMPLE_DEVICE__ - -#include -#include -#include -#include "nehalem.h" - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - u32 pciexbar = 0; - u32 pciexbar_reg; - int max_buses; - - pciexbar_reg = pci_read_config32(PCI_DEV(QUICKPATH_BUS, 0, 1), 0x50); - - // MMCFG not supported or not enabled. - if (!(pciexbar_reg & (1 << 0))) - return current; - - switch ((pciexbar_reg >> 1) & 3) { - case 0: // 256MB - pciexbar = - pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | - (1 << 28)); - max_buses = 256; - break; - case 1: // 128M - pciexbar = - pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | - (1 << 28) | (1 << 27)); - max_buses = 128; - break; - case 2: // 64M - pciexbar = - pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | - (1 << 28) | (1 << 27) | (1 << 26)); - max_buses = 64; - break; - default: // RSVD - return current; - } - - if (!pciexbar) - return current; - - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, - pciexbar, 0x0, 0x0, max_buses - 1); - - return current; -} -- cgit v1.2.3