From 92fc072c2faf3d1be82f50ee3feda42461e9ac16 Mon Sep 17 00:00:00 2001 From: Alexander Couzens Date: Wed, 9 Mar 2016 14:36:46 +0100 Subject: northbridge/intel: move mrccache.c of sandybridge + haswell to common The sourcecode is 99% the same. Only two lines differ, but not in functionality. Also rename mrccache.c -> mrc_cache.c Tested-on: boot + suspend/resume on x220 Change-Id: I36f79d066336f223b608c70c847ea6ea6e4ad287 Signed-off-by: Alexander Couzens Reviewed-on: https://review.coreboot.org/14007 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/northbridge/intel/nehalem/Makefile.inc | 2 -- 1 file changed, 2 deletions(-) (limited to 'src/northbridge/intel/nehalem/Makefile.inc') diff --git a/src/northbridge/intel/nehalem/Makefile.inc b/src/northbridge/intel/nehalem/Makefile.inc index 5d49f5c671..17bbaffe3a 100644 --- a/src/northbridge/intel/nehalem/Makefile.inc +++ b/src/northbridge/intel/nehalem/Makefile.inc @@ -21,12 +21,10 @@ ramstage-y += smi.c ramstage-y += gma.c ramstage-y += acpi.c -ramstage-y += ../sandybridge/mrccache.c romstage-y += ram_calc.c romstage-y += raminit.c romstage-y += early_init.c -romstage-y += ../sandybridge/mrccache.c romstage-y += ../../../arch/x86/walkcbfs.S smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c -- cgit v1.2.3