From 45008930626bda902c8f37880e6f09d517b8cdd2 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Wed, 22 Jul 2020 16:43:48 +0200 Subject: nb/intel/ironlake: Correct PCIEXBAR definition This register resides within the SAD's config space, and is 64-bit. Change-Id: I19458f7c6be6b1a5fcd47ac93ee0597f1251a770 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/43733 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/northbridge/intel/ironlake/acpi.c | 2 +- src/northbridge/intel/ironlake/bootblock.c | 4 ++-- src/northbridge/intel/ironlake/hostbridge_regs.h | 1 - src/northbridge/intel/ironlake/ironlake.h | 2 ++ 4 files changed, 5 insertions(+), 4 deletions(-) (limited to 'src/northbridge/intel/ironlake') diff --git a/src/northbridge/intel/ironlake/acpi.c b/src/northbridge/intel/ironlake/acpi.c index 1fa7267ebe..c954086afb 100644 --- a/src/northbridge/intel/ironlake/acpi.c +++ b/src/northbridge/intel/ironlake/acpi.c @@ -13,7 +13,7 @@ unsigned long acpi_fill_mcfg(unsigned long current) u32 pciexbar_reg; int max_buses; - pciexbar_reg = pci_read_config32(QPI_SAD, 0x50); + pciexbar_reg = pci_read_config32(QPI_SAD, SAD_PCIEXBAR); // MMCFG not supported or not enabled. if (!(pciexbar_reg & (1 << 0))) diff --git a/src/northbridge/intel/ironlake/bootblock.c b/src/northbridge/intel/ironlake/bootblock.c index 50e7adbb93..89eb81339e 100644 --- a/src/northbridge/intel/ironlake/bootblock.c +++ b/src/northbridge/intel/ironlake/bootblock.c @@ -6,6 +6,6 @@ void bootblock_early_northbridge_init(void) { - pci_io_write_config32(QPI_SAD, 0x50, CONFIG_MMCONF_BASE_ADDRESS | 1); - pci_io_write_config32(QPI_SAD, 0x54, 0); + pci_io_write_config32(QPI_SAD, SAD_PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS | 1); + pci_io_write_config32(QPI_SAD, SAD_PCIEXBAR + 4, 0); } diff --git a/src/northbridge/intel/ironlake/hostbridge_regs.h b/src/northbridge/intel/ironlake/hostbridge_regs.h index b835736e4c..a681734c13 100644 --- a/src/northbridge/intel/ironlake/hostbridge_regs.h +++ b/src/northbridge/intel/ironlake/hostbridge_regs.h @@ -11,7 +11,6 @@ #define DEVEN_PEG10 (1 << 1) #define DEVEN_HOST (1 << 0) -#define PCIEXBAR 0x60 #define DMIBAR 0x68 #define LAC 0x87 /* Legacy Access Control */ diff --git a/src/northbridge/intel/ironlake/ironlake.h b/src/northbridge/intel/ironlake/ironlake.h index dd8de97f0a..afd30823d5 100644 --- a/src/northbridge/intel/ironlake/ironlake.h +++ b/src/northbridge/intel/ironlake/ironlake.h @@ -55,6 +55,8 @@ #define QPD0F1_PAM(x) (0x40 + (x)) /* 0-6 */ #define QPD0F1_SMRAM 0x4d /* System Management RAM Control */ +#define SAD_PCIEXBAR 0x50 + /* Device 0:2.0 PCI configuration space (Graphics Device) */ -- cgit v1.2.3