From 1110b2f4620380e6fad6efce30a33bb6739df77b Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 15 Sep 2020 00:03:35 +0200 Subject: nb/intel/ironlake: Drop casts from DEFAULT_{MCHBAR,DMIBAR} There's no need to wrap these macros with casts. Removing them allows dropping more casts in `early_init.c`. To avoid binary changes the casts are put into the {MCH,DMI,EP}BAR{8,16,32} macros instead where they are needed to reach the right memory locations. Change-Id: Icff7919f7321a08338db2f0a765ebd605fd00ae2 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/45378 Tested-by: build bot (Jenkins) --- src/northbridge/intel/ironlake/early_init.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/northbridge/intel/ironlake/early_init.c') diff --git a/src/northbridge/intel/ironlake/early_init.c b/src/northbridge/intel/ironlake/early_init.c index fa89bd9e45..e0120fe078 100644 --- a/src/northbridge/intel/ironlake/early_init.c +++ b/src/northbridge/intel/ironlake/early_init.c @@ -19,9 +19,9 @@ static void ironlake_setup_bars(void) /* Set up all hardcoded northbridge BARs */ pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1); pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR + 4, 0); - pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1); + pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, DEFAULT_MCHBAR | 1); pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4, 0); - pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1); + pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, DEFAULT_DMIBAR | 1); pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, 0); /* Set C0000-FFFFF to access RAM on both reads and writes */ -- cgit v1.2.3