From 45008930626bda902c8f37880e6f09d517b8cdd2 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Wed, 22 Jul 2020 16:43:48 +0200 Subject: nb/intel/ironlake: Correct PCIEXBAR definition This register resides within the SAD's config space, and is 64-bit. Change-Id: I19458f7c6be6b1a5fcd47ac93ee0597f1251a770 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/43733 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/northbridge/intel/ironlake/bootblock.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/northbridge/intel/ironlake/bootblock.c') diff --git a/src/northbridge/intel/ironlake/bootblock.c b/src/northbridge/intel/ironlake/bootblock.c index 50e7adbb93..89eb81339e 100644 --- a/src/northbridge/intel/ironlake/bootblock.c +++ b/src/northbridge/intel/ironlake/bootblock.c @@ -6,6 +6,6 @@ void bootblock_early_northbridge_init(void) { - pci_io_write_config32(QPI_SAD, 0x50, CONFIG_MMCONF_BASE_ADDRESS | 1); - pci_io_write_config32(QPI_SAD, 0x54, 0); + pci_io_write_config32(QPI_SAD, SAD_PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS | 1); + pci_io_write_config32(QPI_SAD, SAD_PCIEXBAR + 4, 0); } -- cgit v1.2.3