From cd49cce7b70e80b4acc49b56bb2bb94370b4d867 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Tue, 5 Mar 2019 16:53:33 -0800 Subject: coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX) This patch is a raw application of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/northbridge/intel/i945/early_init.c | 14 +++++------ src/northbridge/intel/i945/gma.c | 12 ++++----- src/northbridge/intel/i945/raminit.c | 44 ++++++++++++++++----------------- src/northbridge/intel/i945/raminit.h | 2 +- 4 files changed, 36 insertions(+), 36 deletions(-) (limited to 'src/northbridge/intel/i945') diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 1913b524a5..7ab252585a 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -93,7 +93,7 @@ static void i945m_detect_chipset(void) } printk(BIOS_DEBUG, "\n"); - if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) + if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) printk(BIOS_ERR, "coreboot is compiled for the wrong chipset.\n"); } @@ -143,7 +143,7 @@ static void i945_detect_chipset(void) } printk(BIOS_DEBUG, "\n"); - if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) + if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) printk(BIOS_ERR, "coreboot is compiled for the wrong chipset.\n"); } @@ -237,7 +237,7 @@ static void i945_setup_egress_port(void) /* Egress Port Virtual Channel 1 Configuration */ reg32 = EPBAR32(0x2c); reg32 &= 0xffffff00; - if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { + if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { if ((MCHBAR32(CLKCFG) & 7) == 0) reg32 |= 0x1a; /* 1067MHz */ } @@ -256,7 +256,7 @@ static void i945_setup_egress_port(void) reg32 |= (0x0a << 16); EPBAR32(EPVC1RCAP) = reg32; - if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { + if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { if ((MCHBAR32(CLKCFG) & 7) == 0) { /* 1067MHz */ EPBAR32(EPVC1IST + 0) = 0x01380138; EPBAR32(EPVC1IST + 4) = 0x01380138; @@ -941,14 +941,14 @@ void i945_late_initialization(int s3resume) i945_setup_dmi_rcrb(); - if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) + if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) i945_setup_pci_express_x16(); i945_setup_root_complex_topology(); -#if !IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) +#if !CONFIG(HAVE_ACPI_RESUME) #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 -#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) +#if CONFIG(DEBUG_RAM_SETUP) sdram_dump_mchbar_registers(); { diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 26b6c84352..633b09d31b 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -236,9 +236,9 @@ static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf, BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2)) / (pixel_n + 2) / (pixel_p1 * pixel_p2)); - printk(BIOS_INFO, "VGA mode: %s\n", IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER) ? + printk(BIOS_INFO, "VGA mode: %s\n", CONFIG(LINEAR_FRAMEBUFFER) ? "Linear framebuffer" : "text"); - if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) { + if (CONFIG(LINEAR_FRAMEBUFFER)) { /* Disable panel fitter (we're in native resolution). */ write32(mmiobase + PF_CTL(0), 0); write32(mmiobase + PF_WIN_SZ(0), 0); @@ -301,7 +301,7 @@ static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf, ((vactive + bottom_border + vfront_porch + vsync - 1) << 16) | (vactive + bottom_border + vfront_porch - 1)); - if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) { + if (CONFIG(LINEAR_FRAMEBUFFER)) { write32(mmiobase + PIPESRC(1), ((hactive - 1) << 16) | (vactive - 1)); } else { @@ -380,7 +380,7 @@ static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf, else printk(BIOS_ERR, "ERROR: GTT is still Disabled!!!\n"); - if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) { + if (CONFIG(LINEAR_FRAMEBUFFER)) { printk(BIOS_SPEW, "memset %p to 0x00 for %d bytes\n", (void *)pgfx, hactive * vactive * 4); memset((void *)pgfx, 0x00, hactive * vactive * 4); @@ -660,7 +660,7 @@ static void gma_ngi(struct device *const dev) int err; - if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) + if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) panel_setup(mmiobase, dev); /* probe if VGA is connected and always run */ @@ -704,7 +704,7 @@ static void gma_func0_init(struct device *dev) int vga_disable = (pci_read_config16(dev, GGC) & 2) >> 1; - if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) { + if (CONFIG(MAINBOARD_DO_NATIVE_VGA_INIT)) { if (acpi_is_wakeup_s3()) { printk(BIOS_INFO, "Skipping native VGA initialization when resuming from ACPI S3.\n"); diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index a9bfde7805..a93cf1e718 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -33,7 +33,7 @@ #include /* Debugging macros. */ -#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) +#if CONFIG(DEBUG_RAM_SETUP) #define PRINTK_DEBUG(x...) printk(BIOS_DEBUG, x) #else #define PRINTK_DEBUG(x...) @@ -96,7 +96,7 @@ static void ram_read32(u32 offset) read32((void *)offset); } -#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) +#if CONFIG(DEBUG_RAM_SETUP) void sdram_dump_mchbar_registers(void) { int i; @@ -112,7 +112,7 @@ void sdram_dump_mchbar_registers(void) static int memclk(void) { - int offset = IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM) ? 1 : 0; + int offset = CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM) ? 1 : 0; switch (((MCHBAR32(CLKCFG) >> 4) & 7) - offset) { case 1: return 400; @@ -127,7 +127,7 @@ static int memclk(void) static u16 fsbclk(void) { - if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) { + if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) { switch (MCHBAR32(CLKCFG) & 7) { case 0: return 400; case 1: return 533; @@ -137,7 +137,7 @@ static u16 fsbclk(void) MCHBAR32(CLKCFG) & 7); } return 0xffff; - } else if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { + } else if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { switch (MCHBAR32(CLKCFG) & 7) { case 0: return 1066; case 1: return 533; @@ -386,7 +386,7 @@ static void gather_common_timing(struct sys_info *sysinfo, bytes_read = i2c_eeprom_read(device, 0, 64, raw_spd); printk(BIOS_DEBUG, "Reading SPD using i2c block operation.\n"); - if (IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) && bytes_read > 0) + if (CONFIG(DEBUG_RAM_SETUP) && bytes_read > 0) hexdump(raw_spd, bytes_read); if (bytes_read != 64) { /* Try again with SMBUS byte read */ @@ -394,7 +394,7 @@ static void gather_common_timing(struct sys_info *sysinfo, " trying smbus byte operation.\n"); for (j = 0; j < 64; j++) raw_spd[j] = spd_read_byte(device, j); - if (IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)) + if (CONFIG(DEBUG_RAM_SETUP)) hexdump(raw_spd, 64); } @@ -404,7 +404,7 @@ static void gather_common_timing(struct sys_info *sysinfo, continue; } - if (IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)) + if (CONFIG(DEBUG_RAM_SETUP)) dram_print_spd_ddr2(&dimm_info); if (dimm_info.flags.is_ecc) @@ -841,7 +841,7 @@ static const u32 *slew_group_lookup(int dual_channel, int index) return nc; } -#if IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM) +#if CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM) /* Strength multiplier tables */ static const u8 dual_channel_strength_multiplier[] = { 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11, @@ -896,7 +896,7 @@ static const u8 single_channel_strength_multiplier[] = { 0x33, 0x00, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11, 0x33, 0x00, 0x11, 0x00, 0x44, 0x44, 0x33, 0x11 }; -#elif IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC) +#elif CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC) static const u8 dual_channel_strength_multiplier[] = { 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, @@ -1027,7 +1027,7 @@ static void sdram_program_dll_timings(struct sys_info *sysinfo) MCHBAR16(DQSMT) |= (1 << 13) | (0xc << 0); /* We drive both channels with the same speed */ - if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) { + if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) { switch (sysinfo->memory_frequency) { case 400: channeldll = 0x26262626; break; @@ -1036,7 +1036,7 @@ static void sdram_program_dll_timings(struct sys_info *sysinfo) case 667: channeldll = 0x11111111; break; } - } else if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { + } else if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { switch (sysinfo->memory_frequency) { case 400: channeldll = 0x33333333; break; @@ -1052,7 +1052,7 @@ static void sdram_program_dll_timings(struct sys_info *sysinfo) MCHBAR32(C0R0B00DQST + (i * 0x10) + 4) = channeldll; MCHBAR32(C1R0B00DQST + (i * 0x10) + 0) = channeldll; MCHBAR32(C1R0B00DQST + (i * 0x10) + 4) = channeldll; - if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { + if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { MCHBAR8(C0R0B00DQST + (i * 0x10) + 8) = channeldll & 0xff; MCHBAR8(C1R0B00DQST + (i * 0x10) + 8) = channeldll & 0xff; } @@ -1769,7 +1769,7 @@ static void sdram_program_memory_frequency(struct sys_info *sysinfo) { u32 clkcfg; u8 reg8; - u8 offset = IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM) ? 1 : 0; + u8 offset = CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM) ? 1 : 0; printk(BIOS_DEBUG, "Setting Memory Frequency... "); @@ -1854,7 +1854,7 @@ static void sdram_program_clock_crossing(void) /** * We add the indices according to our clocks from CLKCFG. */ -#if IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM) +#if CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM) static const u32 data_clock_crossing[] = { 0x00100401, 0x00000000, /* DDR400 FSB400 */ 0xffffffff, 0xffffffff, /* nonexistent */ @@ -1899,7 +1899,7 @@ static void sdram_program_clock_crossing(void) 0xffffffff, 0xffffffff, /* nonexistent */ }; -#elif IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC) +#elif CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC) /* i945 G/P */ static const u32 data_clock_crossing[] = { 0xffffffff, 0xffffffff, /* nonexistent */ @@ -2119,7 +2119,7 @@ static void sdram_post_jedec_initialization(struct sys_info *sysinfo) if (sysinfo->interleaved) { reg32 = MCHBAR32(DCC); -#if IS_ENABLED(CONFIG_CHANNEL_XOR_RANDOMIZATION) +#if CONFIG(CHANNEL_XOR_RANDOMIZATION) reg32 &= ~(1 << 10); reg32 |= (1 << 9); #else @@ -2175,7 +2175,7 @@ static void sdram_power_management(struct sys_info *sysinfo) reg32 |= (1 << 12) | (1 << 11); MCHBAR32(C1DRC1) = reg32; - if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) { + if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) { if (i945_silicon_revision() > 1) { /* FIXME bits 5 and 0 only if PCIe graphics is disabled */ u16 peg_bits = (1 << 5) | (1 << 0); @@ -2493,9 +2493,9 @@ static void sdram_enable_memory_clocks(struct sys_info *sysinfo) { u8 clocks[2] = { 0, 0 }; -#if IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM) +#if CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM) #define CLOCKS_WIDTH 2 -#elif IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC) +#elif CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC) #define CLOCKS_WIDTH 3 #endif if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED) @@ -2510,7 +2510,7 @@ static void sdram_enable_memory_clocks(struct sys_info *sysinfo) if (sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED) clocks[1] |= ((1 << CLOCKS_WIDTH)-1) << CLOCKS_WIDTH; -#if IS_ENABLED(CONFIG_OVERRIDE_CLOCK_DISABLE) +#if CONFIG(OVERRIDE_CLOCK_DISABLE) /* Usually system firmware turns off system memory clock signals * to unused SO-DIMM slots to reduce EMI and power consumption. * However, the Kontron 986LCD-M does not like unused clock @@ -2755,7 +2755,7 @@ void sdram_initialize(int boot_path, const u8 *spd_addresses) * Program Graphics Frequency * Set core display and render clock on 945GC to the max */ - if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) + if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) sdram_program_graphics_frequency(&sysinfo); else pci_write_config16(PCI_DEV(0, 2, 0), GCFC, 0x0534); diff --git a/src/northbridge/intel/i945/raminit.h b/src/northbridge/intel/i945/raminit.h index 98bdc02afd..2d1eee6947 100644 --- a/src/northbridge/intel/i945/raminit.h +++ b/src/northbridge/intel/i945/raminit.h @@ -70,7 +70,7 @@ void sdram_initialize(int boot_path, const u8 *sdram_addresses); int fixup_i945_errata(void); void udelay(u32 us); -#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) +#if CONFIG(DEBUG_RAM_SETUP) void sdram_dump_mchbar_registers(void); #endif #endif /* RAMINIT_H */ -- cgit v1.2.3