From 872c9222965909dffdd091e644b03e676ca2754f Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Wed, 3 Jul 2013 09:44:28 +0300 Subject: Fix MMCONF_SUPPORT_DEFAULT for ramstage MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Define at one place whether to use IO 0xcf8/0xcfc or MMIO via MMCONF_BASE_ADDRESS for PCI configuration access funtions in ramstage. The implementation of pci_default_config() always returned with pci_cf8_conf1. This means any PCI configuration access that did not target bus 0 used PCI IO config operations, if PCI MMIO config was not explicitly requested. Change-Id: I3b04f570fe88d022cd60dde8bb98e76bd00fe612 Signed-off-by: Kyösti Mälkki Reviewed-on: http://review.coreboot.org/3606 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones Reviewed-by: Aaron Durbin --- src/northbridge/intel/i945/northbridge.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) (limited to 'src/northbridge/intel/i945') diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 9d97f0c17a..7e21164276 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -185,11 +185,7 @@ static struct device_operations pci_domain_ops = { .enable_resources = NULL, .init = NULL, .scan_bus = pci_domain_scan_bus, -#if CONFIG_MMCONF_SUPPORT_DEFAULT - .ops_pci_bus = &pci_ops_mmconf, -#else - .ops_pci_bus = &pci_cf8_conf1, -#endif + .ops_pci_bus = pci_bus_default_ops, }; static void mc_read_resources(device_t dev) -- cgit v1.2.3