From 837141fa56344e41087ae3f525701b98ca9fed96 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 7 Jul 2020 16:12:26 +0200 Subject: nb/intel/i945/acpi: Tidy up comments and cosmetics Use C-style comments, drop unneeded newlines, add missing commas for consistency and relocate a comment to match the code. Tested with BUILD_TIMELESS=1, Getac P470 remains identical. Change-Id: I37fffb60944c35dfb5e0491bb023babfcf2c6a73 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/43177 Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/northbridge/intel/i945/acpi/hostbridge.asl | 120 ++++++++++++------------- src/northbridge/intel/i945/acpi/peg.asl | 5 +- 2 files changed, 62 insertions(+), 63 deletions(-) (limited to 'src/northbridge/intel/i945') diff --git a/src/northbridge/intel/i945/acpi/hostbridge.asl b/src/northbridge/intel/i945/acpi/hostbridge.asl index 5c202b9573..018e5edb9e 100644 --- a/src/northbridge/intel/i945/acpi/hostbridge.asl +++ b/src/northbridge/intel/i945/acpi/hostbridge.asl @@ -9,205 +9,205 @@ Name(_BBN, 0) Device (MCHC) { - Name(_ADR, 0x00000000) // 0:0.0 + Name(_ADR, 0x00000000) /* 0:0.0 */ OperationRegion(MCHP, PCI_Config, 0x00, 0x100) Field (MCHP, DWordAcc, NoLock, Preserve) { - Offset (0x40), // EPBAR - EPEN, 1, // Enable - , 11, // - EPBR, 20, // EPBAR - - // MCHBAR - MHEN, 1, // Enable - , 13, // - MHBR, 18, // MCHBAR - - // PCIe BAR - PXEN, 1, // Enable - PXSZ, 2, // BAR size - , 23, // - PXBR, 6, // PCIe BAR - - // DMIBAR - DMEN, 1, // Enable - , 11, // - DMBR, 20, // DMIBAR - - // ... - - Offset (0x90), // PAM0 + Offset (0x40), /* EPBAR */ + EPEN, 1, /* Enable */ + , 11, + EPBR, 20, /* EPBAR */ + + /* MCHBAR */ + MHEN, 1, /* Enable */ + , 13, + MHBR, 18, /* MCHBAR */ + + /* PCIe BAR */ + PXEN, 1, /* Enable */ + PXSZ, 2, /* BAR size */ + , 23, + PXBR, 6, /* PCIec BAR */ + + /* DMIBAR */ + DMEN, 1, /* Enable */ + , 11, + DMBR, 20, /* DMIBAR */ + + /* ... */ + + Offset (0x90), /* PAM0 */ , 4, PM0H, 2, , 2, - // PAM1 + /* PAM1 */ PM1L, 2, , 2, PM1H, 2, , 2, - // PAM2 + /* PAM2 */ PM2L, 2, , 2, PM2H, 2, , 2, - // PAM3 + /* PAM3 */ PM3L, 2, , 2, PM3H, 2, , 2, - // PAM4 + /* PAM4 */ PM4L, 2, , 2, PM4H, 2, , 2, - // PAM5 + /* PAM5 */ PM5L, 2, , 2, PM5H, 2, , 2, - // PAM6 + /* PAM6 */ PM6L, 2, , 2, PM6H, 2, , 2, - Offset (0x9c), // Top of Low Used Memory + Offset (0x9c), /* Top of Low Used Memory */ , 3, TLUD, 5, - Offset (0xa0), // Top of Used Memory + Offset (0xa0), /* Top of Used Memory */ TOM, 16, } - } - -// Current Resource Settings Name (MCRS, ResourceTemplate() { - // Bus Numbers + /* Bus Numbers */ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00) - // IO Region 0 + /* IO Region 0 */ DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00) - // PCI Config Space + /* PCI Config Space */ Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) - // IO Region 1 + /* IO Region 1 */ DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01) - // VGA memory (0xa0000-0xbffff) + /* VGA memory (0xa0000-0xbffff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, 0x00020000,,, ASEG) - // OPROM reserved (0xc0000-0xc3fff) + /* OPROM reserved (0xc0000-0xc3fff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, 0x00004000,,, OPR0) - // OPROM reserved (0xc4000-0xc7fff) + /* OPROM reserved (0xc4000-0xc7fff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, 0x00004000,,, OPR1) - // OPROM reserved (0xc8000-0xcbfff) + /* OPROM reserved (0xc8000-0xcbfff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, 0x00004000,,, OPR2) - // OPROM reserved (0xcc000-0xcffff) + /* OPROM reserved (0xcc000-0xcffff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, 0x00004000,,, OPR3) - // OPROM reserved (0xd0000-0xd3fff) + /* OPROM reserved (0xd0000-0xd3fff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, 0x00004000,,, OPR4) - // OPROM reserved (0xd4000-0xd7fff) + /* OPROM reserved (0xd4000-0xd7fff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, 0x00004000,,, OPR5) - // OPROM reserved (0xd8000-0xdbfff) + /* OPROM reserved (0xd8000-0xdbfff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, 0x00004000,,, OPR6) - // OPROM reserved (0xdc000-0xdffff) + /* OPROM reserved (0xdc000-0xdffff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, 0x00004000,,, OPR7) - // BIOS Extension (0xe0000-0xe3fff) + /* BIOS Extension (0xe0000-0xe3fff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, 0x00004000,,, ESG0) - // BIOS Extension (0xe4000-0xe7fff) + /* BIOS Extension (0xe4000-0xe7fff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, 0x00004000,,, ESG1) - // BIOS Extension (0xe8000-0xebfff) + /* BIOS Extension (0xe8000-0xebfff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, 0x00004000,,, ESG2) - // BIOS Extension (0xec000-0xeffff) + /* BIOS Extension (0xec000-0xeffff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000ec000, 0x000effff, 0x00000000, 0x00004000,,, ESG3) - // System BIOS (0xf0000-0xfffff) + /* System BIOS (0xf0000-0xfffff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, 0x00010000,,, FSEG) - // PCI Memory Region (Top of memory-0xfebfffff) + /* PCI Memory Region (Top of memory-0xfebfffff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x00000000, 0xfebfffff, 0x00000000, IO_APIC_ADDR,,, PM01) - // TPM Area (0xfed40000-0xfed44fff) + /* TPM Area (0xfed40000-0xfed44fff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, 0x00005000,,, TPMR) }) +/* Current Resource Settings */ Method (_CRS, 0, Serialized) { - // Find PCI resource area in MCRS + /* Find PCI resource area in MCRS */ CreateDwordField(MCRS, ^PM01._MIN, PMIN) CreateDwordField(MCRS, ^PM01._MAX, PMAX) CreateDwordField(MCRS, ^PM01._LEN, PLEN) - // Fix up PCI memory region: - // Enter actual TOLUD. The TOLUD register contains bits 27-31 of - // the top of memory address. + /* + * Fix up PCI memory region: + * Enter actual TOLUD. The TOLUD register contains bits 27-31 of + * the top of memory address. + */ ShiftLeft (^MCHC.TLUD, 27, PMIN) Add(Subtract(PMAX, PMIN), 1, PLEN) diff --git a/src/northbridge/intel/i945/acpi/peg.asl b/src/northbridge/intel/i945/acpi/peg.asl index f85a22c08b..6a67238317 100644 --- a/src/northbridge/intel/i945/acpi/peg.asl +++ b/src/northbridge/intel/i945/acpi/peg.asl @@ -12,16 +12,15 @@ Device (PEGP) Package() { 0x0000ffff, 0, 0, 16 }, Package() { 0x0000ffff, 1, 0, 17 }, Package() { 0x0000ffff, 2, 0, 18 }, - Package() { 0x0000ffff, 3, 0, 19 } + Package() { 0x0000ffff, 3, 0, 19 }, }) } Else { Return (Package() { Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 } + Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, }) } - } } -- cgit v1.2.3