From 16110e7ffaf417f98bef2a359ec522f6fc160ee5 Mon Sep 17 00:00:00 2001 From: Denis 'GNUtoo' Carikli Date: Tue, 14 Oct 2014 07:33:53 +0200 Subject: i945/gma: Fix wrong comment about the documentation. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The GTT location is documented in the "309219" datasheet. For instance it can be found in the TOLUD register description. The 309219 datasheet is for the "Mobile Intel® 945 Express Chipset Family". It was published in 2008. Change-Id: I75ac095ebc577e031af566963ebffe9ed2587c96 Signed-off-by: Denis 'GNUtoo' Carikli Reviewed-on: http://review.coreboot.org/9622 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/northbridge/intel/i945/gma.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) (limited to 'src/northbridge/intel/i945') diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index cee064081c..e5974c980d 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -58,12 +58,7 @@ static int gtt_setup(void *mmiobase) /* * The Video BIOS places the GTT right below top of memory. - * - * It is not documented in the Intel 945 datasheet, but the Intel - * developers said that it is normally placed there. - * - * TODO: Add option to make the GTT size runtime configurable - */ + */ tom = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), TOLUD) << 24; PGETBL_save = tom - 256 * KiB; PGETBL_save |= PGETBL_ENABLED; -- cgit v1.2.3