From 8cc846897132f6d6baa49118005815aefb5f560f Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Sat, 9 Feb 2013 15:56:04 +0100 Subject: Intel: Replace MSR 0xcd with MSR_FSB_FREQ And move the corresponding #define to speedstep.h Change-Id: I8c884b8ab9ba54e01cfed7647a59deafeac94f2d Signed-off-by: Patrick Georgi Reviewed-on: http://review.coreboot.org/2339 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/northbridge/intel/i945/udelay.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/northbridge/intel/i945/udelay.c') diff --git a/src/northbridge/intel/i945/udelay.c b/src/northbridge/intel/i945/udelay.c index ce5e9d8943..be560085e1 100644 --- a/src/northbridge/intel/i945/udelay.c +++ b/src/northbridge/intel/i945/udelay.c @@ -22,6 +22,7 @@ #include #include #include +#include /* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow. */ static inline void multiply_to_tsc(tsc_t *const tsc, const u32 a, const u32 b) @@ -46,7 +47,7 @@ void udelay(u32 us) u32 fsb = 0, divisor; u32 d; /* ticks per us */ - msr = rdmsr(0xcd); + msr = rdmsr(MSR_FSB_FREQ); switch (msr.lo & 0x07) { case 5: fsb = 400; -- cgit v1.2.3