From 784ffb3db694dd2c964d9a4e1c6657a835b2d141 Mon Sep 17 00:00:00 2001 From: Sven Schnelle Date: Tue, 10 Jan 2012 12:16:38 +0100 Subject: i945: fix tsc udelay() The comparision is the wrong way round: as long as tsc is below tsc1, the timeout is not reached Change-Id: I75de74ef750b5a45be0156efaf10d7239a0b1136 Signed-off-by: Sven Schnelle Reviewed-on: http://review.coreboot.org/530 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/northbridge/intel/i945/udelay.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/northbridge/intel/i945/udelay.c') diff --git a/src/northbridge/intel/i945/udelay.c b/src/northbridge/intel/i945/udelay.c index 6b3882bc18..9170335bd5 100644 --- a/src/northbridge/intel/i945/udelay.c +++ b/src/northbridge/intel/i945/udelay.c @@ -78,7 +78,7 @@ void udelay(u32 us) do { tsc = rdtsc(); - } while ((tsc.hi > tsc1.hi) - || ((tsc.hi == tsc1.hi) && (tsc.lo > tsc1.lo))); + } while ((tsc.hi < tsc1.hi) + || ((tsc.hi == tsc1.hi) && (tsc.lo < tsc1.lo))); } -- cgit v1.2.3