From fe481eb3e5e8e8d39d892bfcfe085bc7d49ff886 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Sat, 3 Aug 2019 21:28:40 +0300 Subject: northbridge/intel: Rename ram_calc.c to memmap.c MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use a name consistent with the more recent soc/intel. Change-Id: Ie69583f28f384eb49517203e1c3867f27e6272de Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34699 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/northbridge/intel/i945/ram_calc.c | 132 ---------------------------------- 1 file changed, 132 deletions(-) delete mode 100644 src/northbridge/intel/i945/ram_calc.c (limited to 'src/northbridge/intel/i945/ram_calc.c') diff --git a/src/northbridge/intel/i945/ram_calc.c b/src/northbridge/intel/i945/ram_calc.c deleted file mode 100644 index ac1499e0fc..0000000000 --- a/src/northbridge/intel/i945/ram_calc.c +++ /dev/null @@ -1,132 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -// Use simple device model for this file even in ramstage -#define __SIMPLE_DEVICE__ - -#include -#include -#include -#include "i945.h" -#include -#include -#include -#include -#include -#include -#include - -/* Decodes TSEG region size to bytes. */ -u32 decode_tseg_size(const u8 esmramc) -{ - if (!(esmramc & 1)) - return 0; - switch ((esmramc >> 1) & 3) { - case 0: - return 1 << 20; - case 1: - return 2 << 20; - case 2: - return 8 << 20; - case 3: - default: - die("Bad TSEG setting.\n"); - } -} - -u32 northbridge_get_tseg_base(void) -{ - uintptr_t tom; - - if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1)) - /* IGD enabled, get top of Memory from BSM register */ - tom = pci_read_config32(PCI_DEV(0, 2, 0), BSM); - else - tom = (pci_read_config8(PCI_DEV(0, 0, 0), TOLUD) & 0xf7) << 24; - - /* subsctract TSEG size */ - tom -= decode_tseg_size(pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC)); - return tom; -} - -u32 northbridge_get_tseg_size(void) -{ - const u8 esmramc = pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC); - return decode_tseg_size(esmramc); -} - -/* - * Depending of UMA and TSEG configuration, TSEG might start at any - * 1 MiB alignment. As this may cause very greedy MTRR setup, push - * CBMEM top downwards to 4 MiB boundary. - */ -void *cbmem_top(void) -{ - uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); - return (void *) top_of_ram; -} - -/** Decodes used Graphics Mode Select (GMS) to kilobytes. */ -u32 decode_igd_memory_size(const u32 gms) -{ - static const u16 ggc2uma[] = { 0, 1, 4, 8, 16, 32, - 48, 64 }; - - if (gms >= ARRAY_SIZE(ggc2uma)) - die("Bad Graphics Mode Select (GMS) setting.\n"); - - return ggc2uma[gms] << 10; -} - -void stage_cache_external_region(void **base, size_t *size) -{ - /* The stage cache lives at the end of the TSEG region. - * The top of RAM is defined to be the TSEG base address. - */ - *size = CONFIG_SMM_RESERVED_SIZE; - *base = (void *)((uintptr_t)northbridge_get_tseg_base() - + northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE); -} - -/* platform_enter_postcar() determines the stack to use after - * cache-as-ram is torn down as well as the MTRR settings to use, - * and continues execution in postcar stage. */ -void platform_enter_postcar(void) -{ - struct postcar_frame pcf; - uintptr_t top_of_ram; - - if (postcar_frame_init(&pcf, 0)) - die("Unable to initialize postcar frame.\n"); - - /* Cache the ROM as WP just below 4GiB. */ - postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); - - /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ - postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); - - /* Cache 8 MiB region below the top of ram and 2 MiB above top of - * ram to cover both cbmem as the TSEG region. - */ - top_of_ram = (uintptr_t)cbmem_top(); - postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, - MTRR_TYPE_WRBACK); - postcar_frame_add_mtrr(&pcf, northbridge_get_tseg_base(), - northbridge_get_tseg_size(), MTRR_TYPE_WRBACK); - - run_postcar_phase(&pcf); - - /* We do not return here. */ -} -- cgit v1.2.3