From 62902ca45de871aa59657dd8ec1858c301595634 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 29 Nov 2016 14:13:43 +0100 Subject: sb/ich7: Use common/gpio.h to set up GPIOs This is more consistent with newer Intel targets. This a static struct so it is initialized to 0 by default. To make it more readable: * only setting to GPIO mode is made explicit; * only pins in GPIO mode are either set to input or output since this is ignored in native mode; * only output pins are set high or low, since this is read-only on input; * blink is only operational on output pins, non-blink is not set explicitly; * invert is only operational on input pins, non-invert is not set explicitly. Change-Id: I05f9c52dee78b7120b225982c040e3dcc8ee3e4e Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/17639 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Patrick Rudolph Reviewed-by: Paul Menzel --- src/northbridge/intel/i945/early_init.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/northbridge/intel/i945/early_init.c') diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 8930cb6326..81a6c83207 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -25,6 +25,7 @@ #include #include "i945.h" #include +#include int i945_silicon_revision(void) { @@ -163,7 +164,7 @@ static void i945_setup_bars(void) pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1); pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c /* GC */ , 0x10); /* Enable GPIOs */ - setup_ich7_gpios(); + setup_pch_gpios(&mainboard_gpio_map); printk(BIOS_DEBUG, " done.\n"); printk(BIOS_DEBUG, "Disabling Watchdog reboot..."); -- cgit v1.2.3