From 346d201d73d51ae0a037f64b1bc6d530745b5d4a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sat, 23 Mar 2019 10:07:16 +0200 Subject: nb/intel/i945: Use DEBUG_RAM_SETUP MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Avoid preprocessor here, also we never set loglevel to value of >8 so the call would not be made. The calls to ram_check() were removed, for a long time that function has not tested start..stop region. Change-Id: Ib952b8905c29a5c5c289027071eb6ff59aaa330b Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/32032 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: Angel Pons Reviewed-by: Arthur Heymans --- src/northbridge/intel/i945/early_init.c | 18 ++---------------- 1 file changed, 2 insertions(+), 16 deletions(-) (limited to 'src/northbridge/intel/i945/early_init.c') diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index d3ed27745d..08dd6752d6 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -940,22 +940,8 @@ void i945_late_initialization(int s3resume) i945_setup_root_complex_topology(); -#if !CONFIG(HAVE_ACPI_RESUME) -#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 -#if CONFIG(DEBUG_RAM_SETUP) - sdram_dump_mchbar_registers(); - - { - /* This will not work if TSEG is in place! */ - u32 tom = pci_read_config32(PCI_DEV(0, 2, 0), BSM); - - printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom); - ram_check(0x00000000, 0x000a0000); - ram_check(0x00100000, tom); - } -#endif -#endif -#endif + if (CONFIG(DEBUG_RAM_SETUP)) + sdram_dump_mchbar_registers(); MCHBAR16(SSKPD) = 0xCAFE; -- cgit v1.2.3