From 96184e9f2d911bb8346b90bb2052b7da090b533b Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 9 May 2018 21:23:25 +0200 Subject: nb/intel/i945/bootblock.c: Correct comment Change-Id: Ic28ff80eb1dae6d0a307e2a1b73e8129fffbac13 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/26207 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/northbridge/intel/i945/bootblock.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/northbridge/intel/i945/bootblock.c') diff --git a/src/northbridge/intel/i945/bootblock.c b/src/northbridge/intel/i945/bootblock.c index 4c3c90c49b..1b70df57d3 100644 --- a/src/northbridge/intel/i945/bootblock.c +++ b/src/northbridge/intel/i945/bootblock.c @@ -9,8 +9,8 @@ static void bootblock_northbridge_init(void) /* * The "io" variant of the config access is explicitly used to - * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to - * to true. That way all subsequent non-explicit config accesses use + * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to true. + * That way all subsequent non-explicit config accesses use * MCFG. This code also assumes that bootblock_northbridge_init() is * the first thing called in the non-asm boot block code. The final * assumption is that no assembly code is using the -- cgit v1.2.3