From b6b29dbbb9126f80b592f7856cd09882c231e745 Mon Sep 17 00:00:00 2001 From: Andreas Schultz Date: Mon, 30 Aug 2010 16:19:04 +0000 Subject: Rework i855GM/i855GME support Signed-off-by: Andreas Schultz Acked-by: Stefan Reinauer --- src/northbridge/intel/i855/Kconfig | 30 + src/northbridge/intel/i855/i855.h | 76 +++ src/northbridge/intel/i855/northbridge.c | 21 + src/northbridge/intel/i855/raminit.c | 1036 +++++++++++++++++++++++++----- src/northbridge/intel/i855/raminit.h | 14 +- 5 files changed, 1002 insertions(+), 175 deletions(-) create mode 100644 src/northbridge/intel/i855/i855.h git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5751 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/northbridge/intel/i855/raminit.h | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) (limited to 'src/northbridge/intel/i855/raminit.h') diff --git a/src/northbridge/intel/i855/raminit.h b/src/northbridge/intel/i855/raminit.h index dbd0be6927..1f1b34d14b 100644 --- a/src/northbridge/intel/i855/raminit.h +++ b/src/northbridge/intel/i855/raminit.h @@ -18,11 +18,19 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef RAMINIT_H -#define RAMINIT_H +#ifndef NORTHBRIDGE_INTEL_I855_RAMINIT_H +#define NORTHBRIDGE_INTEL_I855_RAMINIT_H +/* i855 Northbridge PCI device */ +#define NORTHBRIDGE PCI_DEV(0, 0, 0) +#define NORTHBRIDGE_MMC PCI_DEV(0, 0, 1) + +/* The i855 supports max. 2 dual-sided SO-DIMMs. */ #define DIMM_SOCKETS 2 +/* DIMM0 is at 0x50, DIMM1 is at 0x51. */ +#define DIMM_SPD_BASE 0x50 + struct mem_controller { device_t d0; uint16_t channel0[DIMM_SOCKETS]; @@ -31,4 +39,4 @@ struct mem_controller { void sdram_initialize(int controllers, const struct mem_controller *ctrl); -#endif /* RAMINIT_H */ +#endif /* NORTHBRIDGE_INTEL_I855_RAMINIT_H */ -- cgit v1.2.3