From 572d66abb695f8b0dc4f6bec0631ba961cd5b66b Mon Sep 17 00:00:00 2001
From: Keith Hui <buurin@gmail.com>
Date: Tue, 5 May 2020 23:00:48 -0400
Subject: nb/intel/i440bx: Add PMCR register to ACPI code

p3b-f suspend code is going to use it.

Change-Id: Iebc17257e9f690115ec35d94c7c36df39341f0df
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41092
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'src/northbridge/intel/i440bx')

diff --git a/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl b/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl
index ce71aedaee..98d06fb8e1 100644
--- a/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl
+++ b/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl
@@ -9,6 +9,8 @@ Device (NB)
 	{
 		Offset (0x67),	// DRB7
 		DRB7,	8,
+		Offset (0x7A),	// PMCR
+		PMCR,	8
 	}
 	Method(TOM1, 0) {
 		/* Multiply by 8MB to get TOM */
-- 
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