From b91a0f2b83ac7816dc28cac8d3ae13a7d5576864 Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Fri, 15 Jun 2012 15:34:24 -0700 Subject: Rename cache_lbmem() to cache_ramstage() ... and don't require it to specify a cache type. This function is only used on romcc boards, and should go away (because all boards should be switched to CAR) Change-Id: Ic32ca3be1afffc773c72c140e88b338d48a0c8ca Signed-off-by: Stefan Reinauer Reviewed-on: http://review.coreboot.org/1288 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich --- src/northbridge/intel/i3100/raminit.c | 2 +- src/northbridge/intel/i3100/raminit_ep80579.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'src/northbridge/intel/i3100') diff --git a/src/northbridge/intel/i3100/raminit.c b/src/northbridge/intel/i3100/raminit.c index 050df951e5..b453e8ba87 100644 --- a/src/northbridge/intel/i3100/raminit.c +++ b/src/northbridge/intel/i3100/raminit.c @@ -1198,6 +1198,6 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) /* The memory is now setup, use it */ #if !CONFIG_CACHE_AS_RAM - cache_lbmem(MTRR_TYPE_WRBACK); + cache_ramstage(); #endif } diff --git a/src/northbridge/intel/i3100/raminit_ep80579.c b/src/northbridge/intel/i3100/raminit_ep80579.c index 79fc5f72e2..5fe206ff2a 100644 --- a/src/northbridge/intel/i3100/raminit_ep80579.c +++ b/src/northbridge/intel/i3100/raminit_ep80579.c @@ -772,7 +772,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) pci_write_config32(ctrl->f0, DRC, drc); /* The memory is now set up--use it */ - cache_lbmem(MTRR_TYPE_WRBACK); + cache_ramstage(); } static inline int memory_initialized(void) -- cgit v1.2.3