From 8cc846897132f6d6baa49118005815aefb5f560f Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Sat, 9 Feb 2013 15:56:04 +0100 Subject: Intel: Replace MSR 0xcd with MSR_FSB_FREQ And move the corresponding #define to speedstep.h Change-Id: I8c884b8ab9ba54e01cfed7647a59deafeac94f2d Signed-off-by: Patrick Georgi Reviewed-on: http://review.coreboot.org/2339 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/northbridge/intel/i3100/raminit_ep80579.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'src/northbridge/intel/i3100/raminit_ep80579.c') diff --git a/src/northbridge/intel/i3100/raminit_ep80579.c b/src/northbridge/intel/i3100/raminit_ep80579.c index 5fe206ff2a..4c688d55e9 100644 --- a/src/northbridge/intel/i3100/raminit_ep80579.c +++ b/src/northbridge/intel/i3100/raminit_ep80579.c @@ -20,6 +20,7 @@ #include #include +#include #include "raminit_ep80579.h" #include "ep80579.h" @@ -441,8 +442,8 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, /* TODO check: */ /* set front side bus speed */ - msr = rdmsr(0xcd); /* returns 0 on Pentium M 90nm */ - print_debug("msr 0xcd = "); + msr = rdmsr(MSR_FSB_FREQ); /* returns 0 on Pentium M 90nm */ + print_debug("MSR FSB_FREQ(0xcd) = "); print_debug_hex32(msr.hi); print_debug_hex32(msr.lo); print_debug("\n"); -- cgit v1.2.3