From f48acbda7be7074938c06db8ad37705f850661ee Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Fri, 24 Jul 2020 12:24:27 -0600 Subject: src: Change BOOL CONFIG_ to CONFIG() in comments & strings The Kconfig lint tool checks for cases of the code using BOOL type Kconfig options directly instead of with CONFIG() and will print out warnings about it. It gets confused by these references in comments and strings. To fix it so that it can find the real issues, just update these as we would with real issues. Signed-off-by: Martin Roth Change-Id: I5c37f0ee103721c97483d07a368c0b813e3f25c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43824 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Angel Pons --- src/northbridge/intel/haswell/bootblock.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/northbridge/intel/haswell') diff --git a/src/northbridge/intel/haswell/bootblock.c b/src/northbridge/intel/haswell/bootblock.c index 41f18be337..59c31aa672 100644 --- a/src/northbridge/intel/haswell/bootblock.c +++ b/src/northbridge/intel/haswell/bootblock.c @@ -10,11 +10,11 @@ void bootblock_early_northbridge_init(void) /* * The "io" variant of the config access is explicitly used to setup the PCIEXBAR - * because CONFIG_MMCONF_SUPPORT is set to true. That way, all subsequent + * because CONFIG(MMCONF_SUPPORT) is set to true. That way, all subsequent * non-explicit config accesses use MCFG. This code also assumes that * bootblock_northbridge_init() is the first thing called in the non-asm * boot block code. The final assumption is that no assembly code is using - * the CONFIG_MMCONF_SUPPORT option to do PCI config acceses. + * the CONFIG(MMCONF_SUPPORT) option to do PCI config acceses. * * The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB. */ -- cgit v1.2.3