From bde6d309dfafe58732ec46314a2d4c08974b62d4 Mon Sep 17 00:00:00 2001 From: Kevin Paul Herbert Date: Wed, 24 Dec 2014 18:43:20 -0800 Subject: x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer On x86, change the type of the address parameter in read8()/read16/read32()/write8()/write16()/write32() to be a pointer, instead of unsigned long. Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330 Signed-off-by: Kevin Paul Herbert Signed-off-by: Alexandru Gagniuc Reviewed-on: http://review.coreboot.org/7784 Tested-by: build bot (Jenkins) --- src/northbridge/intel/haswell/acpi.c | 2 +- src/northbridge/intel/haswell/early_init.c | 4 ++-- src/northbridge/intel/haswell/gma.c | 4 ++-- src/northbridge/intel/haswell/haswell.h | 4 ++++ src/northbridge/intel/haswell/minihd.c | 7 ++++--- 5 files changed, 13 insertions(+), 8 deletions(-) (limited to 'src/northbridge/intel/haswell') diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c index 488170d74a..1b77b645d8 100644 --- a/src/northbridge/intel/haswell/acpi.c +++ b/src/northbridge/intel/haswell/acpi.c @@ -118,7 +118,7 @@ static int init_opregion_vbt(igd_opregion_t *opregion) optionrom_vbt_t *vbt = (optionrom_vbt_t *)(vbios + oprom->vbt_offset); - if (read32((unsigned long)vbt->hdr_signature) != VBT_SIGNATURE) { + if (read32(vbt->hdr_signature) != VBT_SIGNATURE) { printk(BIOS_DEBUG, "VBT not found!\n"); return 1; } diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c index 7f9f1876b1..ef19984014 100644 --- a/src/northbridge/intel/haswell/early_init.c +++ b/src/northbridge/intel/haswell/early_init.c @@ -34,8 +34,8 @@ static void haswell_setup_bars(void) pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR + 4, (0LL+DEFAULT_EPBAR) >> 32); pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, DEFAULT_MCHBAR | 1); pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4, (0LL+DEFAULT_MCHBAR) >> 32); - pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, DEFAULT_DMIBAR | 1); - pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, (0LL+DEFAULT_DMIBAR) >> 32); + pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1); + pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, (0LL+(uintptr_t)DEFAULT_DMIBAR) >> 32); /* Set C0000-FFFFF to access RAM on both reads and writes */ pci_write_config8(PCI_DEV(0, 0x00, 0), PAM0, 0x30); diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 325edbd05b..5d0e8e7245 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -171,14 +171,14 @@ static struct resource *gtt_res = NULL; u32 gtt_read(u32 reg) { u32 val; - val = read32(gtt_res->base + reg); + val = read32(res2mmio(gtt_res, reg, 0)); return val; } void gtt_write(u32 reg, u32 data) { - write32(gtt_res->base + reg, data); + write32(res2mmio(gtt_res, reg, 0), data); } static inline void gtt_rmw(u32 reg, u32 andmask, u32 ormask) diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index d8221a986b..b673f81543 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -32,7 +32,11 @@ /* Northbridge BARs */ #define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */ #define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */ +#ifndef __ACPI__ +#define DEFAULT_DMIBAR ((u8 *)0xfed18000) /* 4 KB */ +#else #define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ +#endif #define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ #include diff --git a/src/northbridge/intel/haswell/minihd.c b/src/northbridge/intel/haswell/minihd.c index 4a38b2855e..f1b137e064 100644 --- a/src/northbridge/intel/haswell/minihd.c +++ b/src/northbridge/intel/haswell/minihd.c @@ -67,7 +67,8 @@ static const u32 minihd_verb_table[] = { static void minihd_init(struct device *dev) { struct resource *res; - u32 base, reg32; + u32 reg32; + u8 *base; int codec_mask, i; /* Find base address */ @@ -75,8 +76,8 @@ static void minihd_init(struct device *dev) if (!res) return; - base = (u32)res->base; - printk(BIOS_DEBUG, "Mini-HD: base = %08x\n", (u32)base); + base = res2mmio(res, 0, 0); + printk(BIOS_DEBUG, "Mini-HD: base = %p\n", base); /* Set Bus Master */ reg32 = pci_read_config32(dev, PCI_COMMAND); -- cgit v1.2.3