From 97f0d81503be2053a544e80b61732ff5d5479ef0 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 23 Oct 2020 10:53:31 +0200 Subject: nb/intel/haswell/finalize.c: Lock PCU DDR PTM This register has a lock bit. The Haswell System Agent BIOS Spec revision 0.6.0 indicates it needs to be set, thus set it. Note that Broadwell already locks this register. Tested on Asrock B85M Pro4, still boots and register is locked. Change-Id: Ie23b825e708edbfc04ec0d7783f868e8632eb608 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46679 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/northbridge/intel/haswell/finalize.c | 1 + src/northbridge/intel/haswell/registers/mchbar.h | 2 ++ 2 files changed, 3 insertions(+) (limited to 'src/northbridge/intel/haswell') diff --git a/src/northbridge/intel/haswell/finalize.c b/src/northbridge/intel/haswell/finalize.c index ca10146584..efbaf68074 100644 --- a/src/northbridge/intel/haswell/finalize.c +++ b/src/northbridge/intel/haswell/finalize.c @@ -18,6 +18,7 @@ void intel_northbridge_haswell_finalize_smm(void) pci_or_config32(HOST_BRIDGE, TOLUD, 1 << 0); MCHBAR32_OR(MMIO_PAVP_MSG, 1 << 0); /* PAVP */ + MCHBAR32_OR(PCU_DDR_PTM_CTL, 1 << 5); /* DDR PTM */ MCHBAR32_OR(UMAGFXCTL, 1 << 0); /* UMA GFX */ MCHBAR32_OR(VTDTRKLCK, 1 << 0); /* VTDTRK */ MCHBAR32_OR(REQLIM, 1UL << 31); diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h index 96d08bfc22..bd99cee585 100644 --- a/src/northbridge/intel/haswell/registers/mchbar.h +++ b/src/northbridge/intel/haswell/registers/mchbar.h @@ -24,6 +24,8 @@ /* PAVP message register. Bit 0 locks PAVP settings, and bits [31..20] are an offset. */ #define MMIO_PAVP_MSG 0x5500 +#define PCU_DDR_PTM_CTL 0x5880 + /* Some power MSRs are also represented in MCHBAR */ #define MCH_PKG_POWER_LIMIT_LO 0x59a0 #define MCH_PKG_POWER_LIMIT_HI 0x59a4 -- cgit v1.2.3