From 82d73e2d5a44bee097d02d41a450f5bfd703bd5b Mon Sep 17 00:00:00 2001 From: Joel Kitching Date: Tue, 30 Apr 2019 13:13:40 +0800 Subject: nb/intel/haswell: correct a typo in Kconfig Change-Id: I115e065ce11946b85571e7233203be68c1789d70 Signed-off-by: Joel Kitching Reviewed-on: https://review.coreboot.org/c/coreboot/+/32518 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner Reviewed-by: Angel Pons --- src/northbridge/intel/haswell/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/northbridge/intel/haswell') diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index 8c1e0b18f7..e1067c5949 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -37,7 +37,7 @@ config HASWELL_VBOOT_IN_BOOTBLOCK Haswell can either start verstage in a separate stage right after the bootblock has run or it can start it after romstage for compatibility reasons. - Haswell however uses a mrc.bin to initialse memory which + Haswell however uses a mrc.bin to initialize memory which needs to be located at a fixed offset. Therefore even with a separate verstage starting after the bootblock that same binary is used meaning a jump is made from RW to the RO region -- cgit v1.2.3