From 77f7a6e3867307a4835c2d0013f73ada079d09d6 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 9 May 2018 17:47:59 +0200 Subject: nb/intel/haswell: Get rid of device_t Use of device_t has been abandoned in ramstage. Change-Id: I10fb736a7406a6571dffce883fb82c2711526762 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/26196 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/northbridge/intel/haswell/acpi.c | 2 +- src/northbridge/intel/haswell/gma.c | 10 ++++----- src/northbridge/intel/haswell/haswell.h | 2 +- src/northbridge/intel/haswell/minihd.c | 3 ++- src/northbridge/intel/haswell/northbridge.c | 32 ++++++++++++++++------------- 5 files changed, 27 insertions(+), 22 deletions(-) (limited to 'src/northbridge/intel/haswell') diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c index 9d76ba8ce2..292219f272 100644 --- a/src/northbridge/intel/haswell/acpi.c +++ b/src/northbridge/intel/haswell/acpi.c @@ -26,7 +26,7 @@ unsigned long acpi_fill_mcfg(unsigned long current) { - device_t dev; + struct device *dev; u32 pciexbar = 0; u32 pciexbar_reg; int max_buses; diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index c7319fbec8..8ffdce84b2 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -487,7 +487,8 @@ static void gma_func0_init(struct device *dev) intel_gma_restore_opregion(); } -static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void gma_set_subsystem(struct device *dev, unsigned vendor, + unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -501,7 +502,7 @@ static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) const struct i915_gpu_controller_info * intel_gma_get_controller_info(void) { - device_t dev = dev_find_slot(0, PCI_DEVFN(0x2,0)); + struct device *dev = dev_find_slot(0, PCI_DEVFN(0x2,0)); if (!dev) { return NULL; } @@ -509,7 +510,7 @@ intel_gma_get_controller_info(void) return &chip->gfx; } -static void gma_ssdt(device_t device) +static void gma_ssdt(struct device *device) { const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); if (!gfx) { @@ -520,8 +521,7 @@ static void gma_ssdt(device_t device) } static unsigned long -gma_write_acpi_tables(struct device *const dev, - unsigned long current, +gma_write_acpi_tables(struct device *const dev, unsigned long current, struct acpi_rsdp *const rsdp) { igd_opregion_t *opregion = (igd_opregion_t *)current; diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index 5f1530aa05..d8868a1016 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -234,7 +234,7 @@ void report_platform_info(void); #include struct acpi_rsdp; -unsigned long northbridge_write_acpi_tables(device_t device, +unsigned long northbridge_write_acpi_tables(struct device *device, unsigned long start, struct acpi_rsdp *rsdp); #endif diff --git a/src/northbridge/intel/haswell/minihd.c b/src/northbridge/intel/haswell/minihd.c index 9e7ce0e94b..d8b4b664eb 100644 --- a/src/northbridge/intel/haswell/minihd.c +++ b/src/northbridge/intel/haswell/minihd.c @@ -103,7 +103,8 @@ static void minihd_init(struct device *dev) } } -static void minihd_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void minihd_set_subsystem(struct device *dev, unsigned vendor, + unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 095c684bec..613e982d1c 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -33,7 +33,8 @@ #include "chip.h" #include "haswell.h" -static int get_pcie_bar(device_t dev, unsigned int index, u32 *base, u32 *len) +static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base, + u32 *len) { u32 pciexbar_reg; u32 mask; @@ -69,7 +70,7 @@ static int get_pcie_bar(device_t dev, unsigned int index, u32 *base, u32 *len) return 0; } -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device *dev) { assign_resources(dev->link_list); } @@ -87,7 +88,7 @@ static struct device_operations pci_domain_ops = { .write_acpi_tables = northbridge_write_acpi_tables, }; -static int get_bar(device_t dev, unsigned int index, u32 *base, u32 *len) +static int get_bar(struct device *dev, unsigned int index, u32 *base, u32 *len) { u32 bar; @@ -106,7 +107,8 @@ static int get_bar(device_t dev, unsigned int index, u32 *base, u32 *len) /* There are special BARs that actually are programmed in the MCHBAR. These * Intel special features, but they do consume resources that need to be * accounted for. */ -static int get_bar_in_mchbar(device_t dev, unsigned int index, u32 *base, u32 *len) +static int get_bar_in_mchbar(struct device *dev, unsigned int index, + u32 *base, u32 *len) { u32 bar; @@ -125,7 +127,7 @@ static int get_bar_in_mchbar(device_t dev, unsigned int index, u32 *base, u32 *l struct fixed_mmio_descriptor { unsigned int index; u32 size; - int (*get_resource)(device_t dev, unsigned int index, + int (*get_resource)(struct device *dev, unsigned int index, u32 *base, u32 *size); const char *description; }; @@ -145,7 +147,7 @@ struct fixed_mmio_descriptor mc_fixed_resources[] = { * Add all known fixed MMIO ranges that hang off the host bridge/memory * controller device. */ -static void mc_add_fixed_mmio_resources(device_t dev) +static void mc_add_fixed_mmio_resources(struct device *dev) { int i; @@ -202,7 +204,8 @@ struct map_entry { const char *description; }; -static void read_map_entry(device_t dev, struct map_entry *entry, uint64_t *result) +static void read_map_entry(struct device *dev, struct map_entry *entry, + uint64_t *result) { uint64_t value; uint64_t mask; @@ -270,7 +273,7 @@ static struct map_entry memory_map[NUM_MAP_ENTRIES] = { [TSEG_REG] = MAP_ENTRY_BASE_32(TSEG, "TESGMB"), }; -static void mc_read_map_entries(device_t dev, uint64_t *values) +static void mc_read_map_entries(struct device *dev, uint64_t *values) { int i; for (i = 0; i < NUM_MAP_ENTRIES; i++) { @@ -278,7 +281,7 @@ static void mc_read_map_entries(device_t dev, uint64_t *values) } } -static void mc_report_map_entries(device_t dev, uint64_t *values) +static void mc_report_map_entries(struct device *dev, uint64_t *values) { int i; for (i = 0; i < NUM_MAP_ENTRIES; i++) { @@ -289,7 +292,7 @@ static void mc_report_map_entries(device_t dev, uint64_t *values) printk(BIOS_DEBUG, "MC MAP: GGC: 0x%x\n", pci_read_config16(dev, GGC)); } -static void mc_add_dram_resources(device_t dev, int *resource_cnt) +static void mc_add_dram_resources(struct device *dev, int *resource_cnt) { unsigned long base_k, size_k; unsigned long touud_k; @@ -382,7 +385,7 @@ static void mc_add_dram_resources(device_t dev, int *resource_cnt) *resource_cnt = index; } -static void mc_read_resources(device_t dev) +static void mc_read_resources(struct device *dev) { int index = 0; const bool vtd_capable = @@ -406,7 +409,8 @@ static void mc_read_resources(device_t dev) mc_add_dram_resources(dev, &index); } -static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device *dev, unsigned vendor, + unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -470,7 +474,7 @@ static const struct pci_driver mc_driver_hsw_ult __pci_driver = { .device = PCI_DEVICE_ID_HSW_ULT, }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device *dev) { bsp_init_and_start_aps(dev->link_list); } @@ -483,7 +487,7 @@ static struct device_operations cpu_bus_ops = { .scan_bus = 0, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { -- cgit v1.2.3